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drivers: intc: Fix for ESP32C6 interrupt sources allocation

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Fix to properly allocate IRQs for interrupt sources over 60.
It also screens out non-allocatable IRQs used by the CPU.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit is contained in:
Raffael Rostagno 2024-05-14 12:33:47 -03:00 • committed by Anas Nashif
commit 67e43f6a81
4 changed files with 124 additions and 23 deletions
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29
soc/espressif/esp32c6/soc_irq.c
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@ -19,7 +19,8 @@
#include <soc.h>
#include <zephyr/arch/riscv/arch.h>
#define ESP32C6_INTSTATUS_SLOT1_THRESHOLD 32
#define ESP32C6_INTSTATUS_REG1_THRESHOLD 32
#define ESP32C6_INTSTATUS_REG2_THRESHOLD 64
void arch_irq_enable(unsigned int irq)
{
@ -38,8 +39,10 @@ int arch_irq_is_enabled(unsigned int irq)
if (irq < 32) {
res = esp_intr_get_enabled_intmask(0) & BIT(irq);
} else {
} else if (irq < 64) {
res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
} else {
res = esp_intr_get_enabled_intmask(2) & BIT(irq - 64);
}
irq_unlock(key);
@ -52,16 +55,30 @@ uint32_t soc_intr_get_next_source(void)
uint32_t status;
uint32_t source;
/* Status register for interrupt sources 0 ~ 31 */
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) &
esp_intr_get_enabled_intmask(0);
if (status) {
source = __builtin_ffs(status) - 1;
} else {
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) &
esp_intr_get_enabled_intmask(1);
source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_SLOT1_THRESHOLD);
goto ret;
}
/* Status register for interrupt sources 32 ~ 63 */
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) &
esp_intr_get_enabled_intmask(1);
if (status) {
source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG1_THRESHOLD);
goto ret;
}
/* Status register for interrupt sources 64 ~ 76 */
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) &
esp_intr_get_enabled_intmask(2);
source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD);
ret:
return source;
}