diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index 1d88fcb1966..26d6a0f56fe 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_FAMILY_ESPRESSIF_ESP32 && !SOC_SERIES_ESP32C3 + default y if SOC_FAMILY_ESPRESSIF_ESP32 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. diff --git a/drivers/interrupt_controller/Kconfig.esp32c3 b/drivers/interrupt_controller/Kconfig.esp32c3 index c6d4b7da88f..f2bb54b0fc8 100644 --- a/drivers/interrupt_controller/Kconfig.esp32c3 +++ b/drivers/interrupt_controller/Kconfig.esp32c3 @@ -3,7 +3,7 @@ config INTC_ESP32C3 bool "ESP32C3 interrupt controller driver" - depends on SOC_SERIES_ESP32C3 + depends on SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 default y help Enables the esp32c3 interrupt controller driver to handle ISR diff --git a/drivers/interrupt_controller/intc_esp32c3.c b/drivers/interrupt_controller/intc_esp32c3.c index 6293afd07f1..575254ecdfa 100644 --- a/drivers/interrupt_controller/intc_esp32c3.c +++ b/drivers/interrupt_controller/intc_esp32c3.c @@ -41,7 +41,34 @@ LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL); #define ESP32C3_INTC_SRCS_PER_IRQ 2 #define ESP32C3_INTC_AVAILABLE_IRQS 30 -static uint32_t esp_intr_enabled_mask[2] = {0, 0}; +#if defined(CONFIG_SOC_SERIES_ESP32C6) + +#define IRQ_NA 0xFF /* IRQ not available */ +#define IRQ_FREE 0xFE + +#define ESP32C6_INTC_SRCS_PER_IRQ 2 +#define ESP32C6_INTC_AVAILABLE_IRQS 31 + +/* For ESP32C6 only CPU peripheral interrupts number + * 1, 2, 5, 6, 8 ~ 31 are available. + * IRQ 31 is reserved for disabled interrupts + */ +static uint8_t esp_intr_irq_alloc[ESP32C6_INTC_AVAILABLE_IRQS][ESP32C6_INTC_SRCS_PER_IRQ] = { + [0] = {IRQ_NA, IRQ_NA}, + [3] = {IRQ_NA, IRQ_NA}, + [4] = {IRQ_NA, IRQ_NA}, + [7] = {IRQ_NA, IRQ_NA}, + [1 ... 2] = {IRQ_FREE, IRQ_FREE}, + [5 ... 6] = {IRQ_FREE, IRQ_FREE}, + [8 ... 30] = {IRQ_FREE, IRQ_FREE} +}; +#endif + +#define STATUS_MASK_NUM 3 + +static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0}; + +#if defined(CONFIG_SOC_SERIES_ESP32C3) static uint32_t esp_intr_find_irq_for_source(uint32_t source) { @@ -62,6 +89,33 @@ static uint32_t esp_intr_find_irq_for_source(uint32_t source) return irq; } +#elif defined(CONFIG_SOC_SERIES_ESP32C6) + +static uint32_t esp_intr_find_irq_for_source(uint32_t source) +{ + uint32_t irq = 0; + + /* First allocate one source per IRQ, then two + * if there are more sources than free IRQs + */ + for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) { + for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) { + if (esp_intr_irq_alloc[i][j] == IRQ_FREE) { + esp_intr_irq_alloc[i][j] = (uint8_t)source; + irq = i; + goto found; + } + } + } + +found: + INTC_LOG("Found IRQ: %d for source: %d", irq, source); + + return irq; +} + +#endif + void esp_intr_initialize(void) { /* IRQ 31 is reserved for disabled interrupts, @@ -75,6 +129,18 @@ void esp_intr_initialize(void) esp_rom_intr_matrix_set(0, i, ESP32C3_INTC_DISABLED_SLOT); } +#if defined(CONFIG_SOC_SERIES_ESP32C6) + /* Clear up IRQ allocation */ + for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) { + for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) { + /* screen out reserved IRQs */ + if (esp_intr_irq_alloc[i][j] != IRQ_NA) { + esp_intr_irq_alloc[i][j] = IRQ_FREE; + } + } + } +#endif + /* set global esp32c3's INTC masking level */ esprv_intc_int_set_threshold(ESP32C3_INTC_DEFAULT_THRESHOLD); } @@ -106,12 +172,14 @@ int esp_intr_alloc(int source, if (source < 32) { esp_intr_enabled_mask[0] |= (1 << source); - } else { + } else if (source < 64) { esp_intr_enabled_mask[1] |= (1 << (source - 32)); + } else if (source < 96) { + esp_intr_enabled_mask[2] |= (1 << (source - 64)); } - INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X", - esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]); + INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", + esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); irq_unlock(key); irq_enable(source); @@ -131,14 +199,28 @@ int esp_intr_disable(int source) source, ESP32C3_INTC_DISABLED_SLOT); +#if defined(CONFIG_SOC_SERIES_ESP32C6) + for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) { + for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) { + if (esp_intr_irq_alloc[i][j] == source) { + esp_intr_irq_alloc[i][j] = IRQ_FREE; + goto freed; + } + } + } +freed: +#endif + if (source < 32) { esp_intr_enabled_mask[0] &= ~(1 << source); - } else { + } else if (source < 64) { esp_intr_enabled_mask[1] &= ~(1 << (source - 32)); + } else if (source < 96) { + esp_intr_enabled_mask[2] &= ~(1 << (source - 64)); } - INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X", - esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]); + INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", + esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); irq_unlock(key); @@ -158,12 +240,14 @@ int esp_intr_enable(int source) if (source < 32) { esp_intr_enabled_mask[0] |= (1 << source); - } else { + } else if (source < 64) { esp_intr_enabled_mask[1] |= (1 << (source - 32)); + } else if (source < 96) { + esp_intr_enabled_mask[2] |= (1 << (source - 64)); } - INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X", - esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]); + INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", + esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); esprv_intc_int_set_priority(irq, ESP32C3_INTC_DEFAULT_PRIO); esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL); @@ -176,12 +260,12 @@ int esp_intr_enable(int source) uint32_t esp_intr_get_enabled_intmask(int status_mask_number) { - INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X", - esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]); + INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", + esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); - if (status_mask_number == 0) { - return esp_intr_enabled_mask[0]; + if (status_mask_number < STATUS_MASK_NUM) { + return esp_intr_enabled_mask[status_mask_number]; } else { - return esp_intr_enabled_mask[1]; + return 0; /* error */ } } diff --git a/soc/espressif/esp32c6/soc_irq.c b/soc/espressif/esp32c6/soc_irq.c index 42e5e47eaf2..6a452ec78b9 100644 --- a/soc/espressif/esp32c6/soc_irq.c +++ b/soc/espressif/esp32c6/soc_irq.c @@ -19,7 +19,8 @@ #include #include -#define ESP32C6_INTSTATUS_SLOT1_THRESHOLD 32 +#define ESP32C6_INTSTATUS_REG1_THRESHOLD 32 +#define ESP32C6_INTSTATUS_REG2_THRESHOLD 64 void arch_irq_enable(unsigned int irq) { @@ -38,8 +39,10 @@ int arch_irq_is_enabled(unsigned int irq) if (irq < 32) { res = esp_intr_get_enabled_intmask(0) & BIT(irq); - } else { + } else if (irq < 64) { res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32); + } else { + res = esp_intr_get_enabled_intmask(2) & BIT(irq - 64); } irq_unlock(key); @@ -52,16 +55,30 @@ uint32_t soc_intr_get_next_source(void) uint32_t status; uint32_t source; + /* Status register for interrupt sources 0 ~ 31 */ status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) & esp_intr_get_enabled_intmask(0); if (status) { source = __builtin_ffs(status) - 1; - } else { - status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) & - esp_intr_get_enabled_intmask(1); - source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_SLOT1_THRESHOLD); + goto ret; } + /* Status register for interrupt sources 32 ~ 63 */ + status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) & + esp_intr_get_enabled_intmask(1); + + if (status) { + source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG1_THRESHOLD); + goto ret; + } + + /* Status register for interrupt sources 64 ~ 76 */ + status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) & + esp_intr_get_enabled_intmask(2); + + source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD); + +ret: return source; }