boards: nucleo: Convert 4 boards to dts based clocks configuration
Convert following boards to dts based clocks configuration: - nucleo_f070rb - nucleo_f334r8 - nucleo_g071rb - nucleo_g431rb Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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e8a465a446
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67dff334e9
8 changed files with 89 additions and 88 deletions
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@ -42,6 +42,26 @@
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};
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};
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};
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};
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&clk_hse {
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hse-bypass;
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clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
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status = "okay";
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};
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&pll {
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clocks = <&clk_hse>;
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prediv = <1>;
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mul = <6>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(48)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -6,9 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
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# Platform Configuration
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# Platform Configuration
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CONFIG_SOC_STM32F070XB=y
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CONFIG_SOC_STM32F070XB=y
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# General Kernel Options
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
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# Serial Drivers
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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@ -22,19 +19,5 @@ CONFIG_PINMUX=y
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# GPIO Controller
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# GPIO Controller
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# Clock configuration
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# Enable clocks
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# HSE configuration
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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# however, the board does not have an external oscillator, so just use
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 48MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_PREDIV1=1
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=6
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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@ -42,6 +42,27 @@
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};
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};
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};
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};
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&clk_hse {
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hse-bypass;
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clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
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status = "okay";
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};
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&pll {
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clocks = <&clk_hse>;
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prediv = <1>;
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mul = <9>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(72)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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apb2-prescaler = <1>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -6,9 +6,6 @@ CONFIG_SOC_SERIES_STM32F3X=y
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# Platform Configuration
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# Platform Configuration
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CONFIG_SOC_STM32F334X8=y
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CONFIG_SOC_STM32F334X8=y
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# General Kernel Options
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Serial Drivers
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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@ -22,20 +19,5 @@ CONFIG_PINMUX=y
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# GPIO Controller
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# GPIO Controller
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# Clock configuration
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# Enable clock
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# HSE configuration
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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# however, the board does not have an external oscillator, so just use
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_PREDIV=1
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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@ -43,6 +43,27 @@
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};
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};
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};
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};
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&clk_hsi{
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -5,9 +5,6 @@ CONFIG_SOC_STM32G071XX=y
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# Enable MPU
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU=y
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# 64MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=64000000
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# Serial Drivers
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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@ -21,17 +18,5 @@ CONFIG_PINMUX=y
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# GPIO Controller
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# GPIO Controller
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# Clock configuration
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# Enables clocks
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
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# produce 64MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=8
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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@ -51,6 +51,29 @@
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};
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};
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};
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};
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&clk_hse{
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clock-frequency = <DT_FREQ_M(24)>;
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status = "okay";
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};
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&pll {
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div-m = <6>;
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mul-n = <85>;
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div-p = <7>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(170)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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&usart1 {
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&usart1 {
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -3,14 +3,6 @@
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CONFIG_SOC_SERIES_STM32G4X=y
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CONFIG_SOC_SERIES_STM32G4X=y
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CONFIG_SOC_STM32G431XX=y
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CONFIG_SOC_STM32G431XX=y
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# 170MHz system clock only in 'boost power' mode.
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# RM0440, section 5.1.5 states that the R1MODE bit
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# must be cleared before system can be 170MHz.
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=170000000
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# 150MHz system clock in 'normal power' mode
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# CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000
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# enable uart driver
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# enable uart driver
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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@ -20,35 +12,9 @@ CONFIG_PINMUX=y
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# enable GPIO
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# enable GPIO
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# clock configuration
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# enable clocks
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# Use PLLCLK for SYSCLK
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# Use HSE (24MHz) to feed into PLL
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=24000000
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
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# Produce 150MHz clock at PLLCLK output
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# CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
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# CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=50
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# Produce 170MHz clock at PLLCLK output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=6
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=85
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# Produce Max (150MHz or 170MHz) HCLK
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# Produce Max (150MHz or 170MHz) APB1 clocks and APB2 clocks
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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# Console
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# Console
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CONFIG_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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