diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb.dts b/boards/arm/nucleo_f070rb/nucleo_f070rb.dts index ae16d8fdb16..601dcba9815 100644 --- a/boards/arm/nucleo_f070rb/nucleo_f070rb.dts +++ b/boards/arm/nucleo_f070rb/nucleo_f070rb.dts @@ -42,6 +42,26 @@ }; }; +&clk_hse { + hse-bypass; + clock-frequency = ; /* STLink 8MHz clock */ + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + prediv = <1>; + mul = <6>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <2>; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; current-speed = <115200>; diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig index efa96b95f9c..bca68ac1f0e 100644 --- a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig +++ b/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig @@ -6,9 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y # Platform Configuration CONFIG_SOC_STM32F070XB=y -# General Kernel Options -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y @@ -22,19 +19,5 @@ CONFIG_PINMUX=y # GPIO Controller CONFIG_GPIO=y -# Clock configuration +# Enable clocks CONFIG_CLOCK_CONTROL=y -# SYSCLK selection -CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y -# HSE configuration -CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 -# however, the board does not have an external oscillator, so just use -# the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32_HSE_BYPASS=y -# PLL configuration -CONFIG_CLOCK_STM32_PLL_SRC_HSE=y -# produce 48MHz clock at PLL output -CONFIG_CLOCK_STM32_PLL_PREDIV1=1 -CONFIG_CLOCK_STM32_PLL_MULTIPLIER=6 -CONFIG_CLOCK_STM32_AHB_PRESCALER=1 -CONFIG_CLOCK_STM32_APB1_PRESCALER=1 diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8.dts b/boards/arm/nucleo_f334r8/nucleo_f334r8.dts index 6a2d9297e82..9ff5a06872f 100644 --- a/boards/arm/nucleo_f334r8/nucleo_f334r8.dts +++ b/boards/arm/nucleo_f334r8/nucleo_f334r8.dts @@ -42,6 +42,27 @@ }; }; +&clk_hse { + hse-bypass; + clock-frequency = ; /* STLink 8MHz clock */ + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + prediv = <1>; + mul = <9>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <2>; + apb2-prescaler = <1>; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; current-speed = <115200>; diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig index c61c938f55d..3d856073346 100644 --- a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig +++ b/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig @@ -6,9 +6,6 @@ CONFIG_SOC_SERIES_STM32F3X=y # Platform Configuration CONFIG_SOC_STM32F334X8=y -# General Kernel Options -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y @@ -22,20 +19,5 @@ CONFIG_PINMUX=y # GPIO Controller CONFIG_GPIO=y -# Clock configuration +# Enable clock CONFIG_CLOCK_CONTROL=y -# SYSCLK selection -CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y -# HSE configuration -CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 -# however, the board does not have an external oscillator, so just use -# the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32_HSE_BYPASS=y -# PLL configuration -CONFIG_CLOCK_STM32_PLL_SRC_HSE=y -# produce 72MHz clock at PLL output -CONFIG_CLOCK_STM32_PLL_PREDIV=1 -CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9 -CONFIG_CLOCK_STM32_AHB_PRESCALER=1 -CONFIG_CLOCK_STM32_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32_APB2_PRESCALER=1 diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts b/boards/arm/nucleo_g071rb/nucleo_g071rb.dts index 05fac55db39..cf71ae64917 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/arm/nucleo_g071rb/nucleo_g071rb.dts @@ -43,6 +43,27 @@ }; }; +&clk_hsi{ + status = "okay"; +}; + +&pll { + div-m = <1>; + mul-n = <8>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>; current-speed = <115200>; diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig b/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig index fb304a03cf6..2fa8573ed2e 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig +++ b/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig @@ -5,9 +5,6 @@ CONFIG_SOC_STM32G071XX=y # Enable MPU CONFIG_ARM_MPU=y -# 64MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=64000000 - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y @@ -21,17 +18,5 @@ CONFIG_PINMUX=y # GPIO Controller CONFIG_GPIO=y -# Clock configuration +# Enables clocks CONFIG_CLOCK_CONTROL=y -# SYSCLK selection -CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y -# PLL configuration -CONFIG_CLOCK_STM32_PLL_SRC_HSI=y -# produce 64MHz clock at PLL output -CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1 -CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=8 -CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 -CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2 -CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 -CONFIG_CLOCK_STM32_AHB_PRESCALER=1 -CONFIG_CLOCK_STM32_APB1_PRESCALER=1 diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb.dts b/boards/arm/nucleo_g431rb/nucleo_g431rb.dts index 1f779f1c8ae..fe6240c4ae1 100644 --- a/boards/arm/nucleo_g431rb/nucleo_g431rb.dts +++ b/boards/arm/nucleo_g431rb/nucleo_g431rb.dts @@ -51,6 +51,29 @@ }; }; +&clk_hse{ + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <6>; + mul-n = <85>; + div-p = <7>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>; current-speed = <115200>; diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig b/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig index 0b3c108c5ca..0892c157d64 100644 --- a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig +++ b/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig @@ -3,14 +3,6 @@ CONFIG_SOC_SERIES_STM32G4X=y CONFIG_SOC_STM32G431XX=y -# 170MHz system clock only in 'boost power' mode. -# RM0440, section 5.1.5 states that the R1MODE bit -# must be cleared before system can be 170MHz. -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=170000000 - -# 150MHz system clock in 'normal power' mode -# CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 - # enable uart driver CONFIG_SERIAL=y @@ -20,35 +12,9 @@ CONFIG_PINMUX=y # enable GPIO CONFIG_GPIO=y -# clock configuration +# enable clocks CONFIG_CLOCK_CONTROL=y -# Use PLLCLK for SYSCLK -CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y - -# Use HSE (24MHz) to feed into PLL -CONFIG_CLOCK_STM32_PLL_SRC_HSE=y -CONFIG_CLOCK_STM32_HSE_CLOCK=24000000 - -CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7 -CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2 -CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 - -# Produce 150MHz clock at PLLCLK output -# CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 -# CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=50 - -# Produce 170MHz clock at PLLCLK output -CONFIG_CLOCK_STM32_PLL_M_DIVISOR=6 -CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=85 - -# Produce Max (150MHz or 170MHz) HCLK -CONFIG_CLOCK_STM32_AHB_PRESCALER=1 - -# Produce Max (150MHz or 170MHz) APB1 clocks and APB2 clocks -CONFIG_CLOCK_STM32_APB1_PRESCALER=1 -CONFIG_CLOCK_STM32_APB2_PRESCALER=1 - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y