nxp_kinetis: Add Kconfig options to configure clocks

Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose
Clock Generator (MCG) module to configure clocks. Adding options to
configure these modules for PLL operation with different external
oscillator frequencies, which can vary across boards. More options may
be added later to support other clocking modes such as FLL.

Jira: ZEP-715
Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

arch/arm/soc/nxp_kinetis/Kconfig

@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2016 Intel Corporation
+# Copyright (c) 2016, Freescale Semiconductor, Inc.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -34,3 +35,75 @@ config SOC_PART_NUMBER
 	This string holds the full part number of the SoC. It is a hidden option
 	that you should not set directly. The part number selection choice defines
 	the default value for this string.
+
+config HAS_OSC
+	bool
+	default n
+	help
+	Set if the oscillator (OSC) module is present in the SoC.
+
+config HAS_MCG
+	bool
+	default n
+	help
+	Set if the multipurpose clock generator (MCG) module is present in the SoC.
+
+if HAS_OSC
+
+choice
+	prompt "Oscillator Mode Selection"
+	default OSC_EXTERNAL
+
+config OSC_EXTERNAL
+	bool "External reference clock"
+	help
+	Set this option to use the oscillator in external reference clock mode.
+
+config OSC_LOW_POWER
+	bool "Low power oscillator"
+	help
+	Set this option to use the oscillator in low-power mode.
+
+config OSC_HIGH_GAIN
+	bool "High gain oscillator"
+	help
+	Set this option to use the oscillator in high-gain mode.
+
+endchoice
+
+config OSC_XTAL0_FREQ
+	int "External oscillator frequency"
+	help
+	Set the external oscillator frequency in Hz. This should be set by the
+	board's defconfig.
+
+endif # HAS_OSC
+
+if HAS_MCG
+
+config MCG_PRDIV0
+	hex "PLL external reference divider"
+	range 0 0x18
+	default 0
+	help
+	Selects the amount to divide down the external reference clock for the PLL.
+	The resulting frequency must be in the range of 2 MHz to 4 MHz.
+
+config MCG_VDIV0
+	hex "VCO 0 divider"
+	range 0 0x1F
+	default 0
+	help
+	Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+	establish the multiplication factor (M) applied to the reference clock
+	frequency.
+
+config MCG_FCRDIV
+	int "Fast internal reference clock divider"
+	range 0 7
+	default 1
+	help
+	Selects the amount to divide down the fast internal reference clock. The
+	resulting frequency must be in the range 31.25 kHz to 4 MHz.
+
+endif # HAS_MCG

arch/arm/soc/nxp_kinetis/k6x/Kconfig.soc

@@ -22,6 +22,8 @@ depends on SOC_SERIES_KINETIS_K6X
 config SOC_MK64F12
 	bool "SOC_MK64F12"
 	select HAS_KSDK
+	select HAS_OSC
+	select HAS_MCG
 	select CPU_HAS_FPU
 
 endchoice

boards/frdm_k64f/Kconfig.defconfig

@@ -1,3 +1,19 @@
+# Kconfig - FRDM-K64F board
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 
 if BOARD_FRDM_K64F
 
@@ -10,4 +26,16 @@ config FLASH_SIZE
 config SRAM_SIZE
 	default 192
 
+config OSC_XTAL0_FREQ
+	default 50000000
+
+config MCG_PRDIV0
+	default 0x13
+
+config MCG_VDIV0
+	default 0x18
+
+config MCG_FCRDIV
+	default 1
+
 endif # BOARD_FRDM_K64F

boards/frdm_k64f/frdm_k64f_defconfig

@@ -9,3 +9,4 @@ CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_UART_K20=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
+CONFIG_OSC_EXTERNAL=y