67132c8689
Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose Clock Generator (MCG) module to configure clocks. Adding options to configure these modules for PLL operation with different external oscillator frequencies, which can vary across boards. More options may be added later to support other clocking modes such as FLL. Jira: ZEP-715 Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
126 lines
3.3 KiB
Text
126 lines
3.3 KiB
Text
# Kconfig - Kinetis K6X MCU line
|
|
#
|
|
# Copyright (c) 2016 Open-RnD Sp. z o.o.
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
|
|
choice
|
|
prompt "Kinetis K6x MCU Selection"
|
|
depends on SOC_SERIES_KINETIS_K6X
|
|
|
|
config SOC_MK64F12
|
|
bool "SOC_MK64F12"
|
|
select HAS_KSDK
|
|
select HAS_OSC
|
|
select HAS_MCG
|
|
select CPU_HAS_FPU
|
|
|
|
endchoice
|
|
|
|
if SOC_SERIES_KINETIS_K6X
|
|
|
|
config SOC_PART_NUMBER_MK64FN1M0CAJ12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FN1M0VDC12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FN1M0VLL12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FN1M0VLQ12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FN1M0VMD12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FX512VDC12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FX512VLL12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FX512VLQ12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MK64FX512VMD12
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_KINETIS_K6X
|
|
string
|
|
default "MK64FN1M0CAJ12" if SOC_PART_NUMBER_MK64FN1M0CAJ12
|
|
default "MK64FN1M0VDC12" if SOC_PART_NUMBER_MK64FN1M0VDC12
|
|
default "MK64FN1M0VLL12" if SOC_PART_NUMBER_MK64FN1M0VLL12
|
|
default "MK64FN1M0VLQ12" if SOC_PART_NUMBER_MK64FN1M0VLQ12
|
|
default "MK64FN1M0VMD12" if SOC_PART_NUMBER_MK64FN1M0VMD12
|
|
default "MK64FX512VDC12" if SOC_PART_NUMBER_MK64FX512VDC12
|
|
default "MK64FX512VLL12" if SOC_PART_NUMBER_MK64FX512VLL12
|
|
default "MK64FX512VLQ12" if SOC_PART_NUMBER_MK64FX512VLQ12
|
|
default "MK64FX512VMD12" if SOC_PART_NUMBER_MK64FX512VMD12
|
|
help
|
|
This string holds the full part number of the SoC. It is a hidden option
|
|
that you should not set directly. The part number selection choice defines
|
|
the default value for this string.
|
|
|
|
config K64_CORE_CLOCK_DIVIDER
|
|
int
|
|
prompt "Freescale K64 core clock divider"
|
|
default 1
|
|
help
|
|
This option specifies the divide value for the K64 processor core clock
|
|
from the system clock.
|
|
|
|
config K64_BUS_CLOCK_DIVIDER
|
|
int
|
|
prompt "Freescale K64 bus clock divider"
|
|
default 2
|
|
help
|
|
This option specifies the divide value for the K64 bus clock from the
|
|
system clock.
|
|
|
|
config K64_FLEXBUS_CLOCK_DIVIDER
|
|
int
|
|
prompt "Freescale K64 FlexBus clock divider"
|
|
default 3
|
|
help
|
|
This option specifies the divide value for the K64 FlexBus clock from the
|
|
system clock.
|
|
|
|
config K64_FLASH_CLOCK_DIVIDER
|
|
int
|
|
prompt "Freescale K64 flash clock divider"
|
|
default 5
|
|
help
|
|
This option specifies the divide value for the K64 flash clock from the
|
|
system clock.
|
|
|
|
config WDOG_INIT
|
|
def_bool y
|
|
# omit prompt to signify a "hidden" option
|
|
help
|
|
This processor enables the watchdog timer with a short timeout
|
|
upon reset. Therefore, this requires that the watchdog be configured
|
|
during reset handling.
|
|
|
|
config PRESERVE_JTAG_IO_PINS
|
|
bool "Kinetis K6x JTAG pin usage"
|
|
depends on PINMUX
|
|
default y
|
|
help
|
|
The FRDM-K64F board routes the PTA0/1/2 pins as JTAG/SWD signals that
|
|
are used for the OpenSDAv2 debug interface. These pins are also routed to
|
|
the Arduino header as D8, D3 and D5, respectively.
|
|
Enable this option to preserve these pins for the debug interface.
|
|
|
|
endif # SOC_SERIES_KINETIS_K6X
|