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boards: mimxrt1160_evk: add support for loading M4 image from OCRAM

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Add support for loading M4 image from OCRAM when running with dual core
operation. The M7 core will copy the M4 image from flash into OCRAM, and
the M4 core will execute it there.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-11-15 15:40:25 -06:00 • committed by Carles Cufí
commit 6688fa2a39
4 changed files with 20 additions and 4 deletions
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16
boards/arm/mimxrt1160_evk/Kconfig.defconfig
View file

@ -11,9 +11,25 @@ config BOARD
choice CODE_LOCATION choice CODE_LOCATION
default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7 default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7
default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX
default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4 default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4
endchoice endchoice
if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4
config BUILD_OUTPUT_INFO_HEADER
default y
DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
# Adjust the offset of the output image if building for RT11xx SOC
config BUILD_OUTPUT_ADJUST_LMA
default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
endif
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK

6
boards/arm/mimxrt1160_evk/board.cmake
View file

@ -4,12 +4,10 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #
if(CONFIG_SOC_MIMXRT1166_CM7) if(CONFIG_SOC_MIMXRT1166_CM7 OR CONFIG_SECOND_CORE_MCUX)
board_runner_args(pyocd "--target=mimxrt1160_cm7") board_runner_args(pyocd "--target=mimxrt1160_cm7")
board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load") board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load")
endif() elseif(CONFIG_SOC_MIMXRT1166_CM4)
if(CONFIG_SOC_MIMXRT1166_CM4)
board_runner_args(pyocd "--target=mimxrt1160_cm4") board_runner_args(pyocd "--target=mimxrt1160_cm4")
# Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
board_runner_args(jlink "--device=MIMXRT1166xxx6_M4") board_runner_args(jlink "--device=MIMXRT1166xxx6_M4")

1
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
View file

@ -25,6 +25,7 @@
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,flash-controller = &is25wp128; zephyr,flash-controller = &is25wp128;
zephyr,flash = &is25wp128; zephyr,flash = &is25wp128;
nxp,m4-partition = &slot1_partition;
}; };

1
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts
View file

@ -23,6 +23,7 @@
zephyr,flash-controller = &is25wp128; zephyr,flash-controller = &is25wp128;
zephyr,flash = &is25wp128; zephyr,flash = &is25wp128;
zephyr,code-partition = &slot0_partition; zephyr,code-partition = &slot0_partition;
zephyr,cpu1-region = &ocram;
}; };
sdram0: memory@80000000 { sdram0: memory@80000000 {