6688fa2a39
Add support for loading M4 image from OCRAM when running with dual core operation. The M7 core will copy the M4 image from flash into OCRAM, and the M4 core will execute it there. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
56 lines
1.4 KiB
Text
56 lines
1.4 KiB
Text
# MIMXRT1160-EVK board
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# Copyright (c) 2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4
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config BOARD
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default "mimxrt1160_evk_cm7" if BOARD_MIMXRT1160_EVK_CM7
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default "mimxrt1160_evk_cm4" if BOARD_MIMXRT1160_EVK_CM4
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choice CODE_LOCATION
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default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7
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default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX
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default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4
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endchoice
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if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4
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config BUILD_OUTPUT_INFO_HEADER
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default y
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DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
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# Adjust the offset of the output image if building for RT11xx SOC
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config BUILD_OUTPUT_ADJUST_LMA
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default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
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$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
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$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
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endif
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
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default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK
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if FLASH
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choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
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default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
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default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
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endchoice
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endif #FLASH
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if NETWORKING
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config NET_L2_ETHERNET
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default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4
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