michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: clock_control: Add support for stm32f2

Browse source 
Add clock control support for the stm32f2

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This commit is contained in:
qianfan Zhao 2018-05-11 21:28:03 +08:00 • committed by Kumar Gala
commit 6091a7fd50
7 changed files with 117 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/soc/st_stm32/stm32f2/Kconfig.series
View file

@ -13,5 +13,6 @@ config SOC_SERIES_STM32F2X
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select HAS_STM32CUBE
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for stm32f2 MCU series

7
arch/arm/soc/st_stm32/stm32f2/soc.h
View file

@ -29,6 +29,13 @@
#include <stm32f2xx.h>
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32f2xx_ll_utils.h>
#include <stm32f2xx_ll_bus.h>
#include <stm32f2xx_ll_rcc.h>
#include <stm32f2xx_ll_system.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F2_SOC_H_ */

1
drivers/clock_control/CMakeLists.txt
View file

@ -9,6 +9,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X stm32f0x_ll_clock.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X stm32f1x_ll_clock.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X stm32f2x_ll_clock.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X stm32f3x_ll_clock.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X stm32f4x_ll_clock.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X stm32f7x_ll_clock.c)

43
drivers/clock_control/Kconfig.stm32
View file

@ -194,6 +194,49 @@ config CLOCK_STM32_PLL2_PREDIV2
endif # SOC_SERIES_STM32F1X
if SOC_SERIES_STM32F2X
config CLOCK_STM32_PLL_M_DIVISOR
int "Division factor for PLL VCO input clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 20
range 2 63
help
PLLM division factor needs to be set correctly to ensure that the VCO
input frequency ranges from 1 to 2 MHz. It is recommended to select a
frequency of 2 MHz to limit PLL jitter.
Allowed values: 2-63
config CLOCK_STM32_PLL_N_MULTIPLIER
int "Multiplier factor for PLL VCO output clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 192
range 192 432
help
PLLN multiplier factor needs to be set correctly to ensure that the
VCO output frequency is between 192 and 432 MHz.
config CLOCK_STM32_PLL_P_DIVISOR
int "PLL division factor for main system clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 2 8
help
PLLP division factor needs to be set correctly to not exceed 120MHz.
Allowed values: 2, 4, 6, 8
config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL division factor for USB OTG FS, SDIO and RNG clocks"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 5
range 2 15
help
The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
need a frequency lower than or equal to 48 MHz to work correctly.
Allowed values: 2-15
endif # SOC_SERIES_STM32F2X
if SOC_SERIES_STM32F3X
config CLOCK_STM32_PLL_PREDIV

6
drivers/clock_control/stm32_ll_clock.c
View file

@ -58,7 +58,8 @@ static inline int stm32_clock_control_on(struct device *dev,
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X)
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
@ -101,7 +102,8 @@ static inline int stm32_clock_control_off(struct device *dev,
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X)
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;

52
drivers/clock_control/stm32f2x_ll_clock.c Normal file
View file

@ -0,0 +1,52 @@
/*
*
* Copyright (c) 2018 qianfan Zhao
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <soc_registers.h>
#include <clock_control.h>
#include <misc/util.h>
#include <clock_control/stm32_clock_control.h>
#include "stm32_ll_clock.h"
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
#define _pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) _pllp(v)
/**
* @brief fill in pll configuration structure
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Power Interface clock enabled by default */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
}
/**
* @brief Function kept for driver genericity
*/
void LL_RCC_MSI_Disable(void)
{
/* Do nothing */
}

9
dts/arm/st/stm32f2.dtsi
View file

@ -7,6 +7,7 @@
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
#include <st/stm32f2-pinctrl.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
/ {
cpus {
@ -39,5 +40,13 @@
write-block-size = <1>;
};
};
rcc: rcc@40023800 {
compatible = "st,stm32-rcc";
clocks-controller;
#clock-cells = <2>;
reg = <0x40023800 0x400>;
label = "STM32_CLK_RCC";
};
};
};