diff --git a/arch/arm/soc/st_stm32/stm32f2/Kconfig.series b/arch/arm/soc/st_stm32/stm32f2/Kconfig.series index 9f035b31110..73b35ed5911 100644 --- a/arch/arm/soc/st_stm32/stm32f2/Kconfig.series +++ b/arch/arm/soc/st_stm32/stm32f2/Kconfig.series @@ -13,5 +13,6 @@ config SOC_SERIES_STM32F2X select SYS_POWER_LOW_POWER_STATE_SUPPORTED select HAS_STM32CUBE select CPU_HAS_SYSTICK + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL help Enable support for stm32f2 MCU series diff --git a/arch/arm/soc/st_stm32/stm32f2/soc.h b/arch/arm/soc/st_stm32/stm32f2/soc.h index 710effde302..3c9f38fa764 100644 --- a/arch/arm/soc/st_stm32/stm32f2/soc.h +++ b/arch/arm/soc/st_stm32/stm32f2/soc.h @@ -29,6 +29,13 @@ #include +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE +#include +#include +#include +#include +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + #endif /* !_ASMLANGUAGE */ #endif /* _STM32F2_SOC_H_ */ diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 7179dfafc3f..e7ef3af5ecc 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -9,6 +9,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X stm32f0x_ll_clock.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X stm32f1x_ll_clock.c) + zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X stm32f2x_ll_clock.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X stm32f3x_ll_clock.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X stm32f4x_ll_clock.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X stm32f7x_ll_clock.c) diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32 index df1a4786d36..c5df35b53be 100644 --- a/drivers/clock_control/Kconfig.stm32 +++ b/drivers/clock_control/Kconfig.stm32 @@ -194,6 +194,49 @@ config CLOCK_STM32_PLL2_PREDIV2 endif # SOC_SERIES_STM32F1X +if SOC_SERIES_STM32F2X + +config CLOCK_STM32_PLL_M_DIVISOR + int "Division factor for PLL VCO input clock" + depends on CLOCK_STM32_SYSCLK_SRC_PLL + default 20 + range 2 63 + help + PLLM division factor needs to be set correctly to ensure that the VCO + input frequency ranges from 1 to 2 MHz. It is recommended to select a + frequency of 2 MHz to limit PLL jitter. + Allowed values: 2-63 + +config CLOCK_STM32_PLL_N_MULTIPLIER + int "Multiplier factor for PLL VCO output clock" + depends on CLOCK_STM32_SYSCLK_SRC_PLL + default 192 + range 192 432 + help + PLLN multiplier factor needs to be set correctly to ensure that the + VCO output frequency is between 192 and 432 MHz. + +config CLOCK_STM32_PLL_P_DIVISOR + int "PLL division factor for main system clock" + depends on CLOCK_STM32_SYSCLK_SRC_PLL + default 2 + range 2 8 + help + PLLP division factor needs to be set correctly to not exceed 120MHz. + Allowed values: 2, 4, 6, 8 + +config CLOCK_STM32_PLL_Q_DIVISOR + int "PLL division factor for USB OTG FS, SDIO and RNG clocks" + depends on CLOCK_STM32_SYSCLK_SRC_PLL + default 5 + range 2 15 + help + The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG + need a frequency lower than or equal to 48 MHz to work correctly. + Allowed values: 2-15 + +endif # SOC_SERIES_STM32F2X + if SOC_SERIES_STM32F3X config CLOCK_STM32_PLL_PREDIV diff --git a/drivers/clock_control/stm32_ll_clock.c b/drivers/clock_control/stm32_ll_clock.c index 99aa1b02c09..6d161b53206 100644 --- a/drivers/clock_control/stm32_ll_clock.c +++ b/drivers/clock_control/stm32_ll_clock.c @@ -58,7 +58,8 @@ static inline int stm32_clock_control_on(struct device *dev, break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_SOC_SERIES_STM32F7X) + defined(CONFIG_SOC_SERIES_STM32F7X) || \ + defined(CONFIG_SOC_SERIES_STM32F2X) case STM32_CLOCK_BUS_AHB2: LL_AHB2_GRP1_EnableClock(pclken->enr); break; @@ -101,7 +102,8 @@ static inline int stm32_clock_control_off(struct device *dev, break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_SOC_SERIES_STM32F7X) + defined(CONFIG_SOC_SERIES_STM32F7X) || \ + defined(CONFIG_SOC_SERIES_STM32F2X) case STM32_CLOCK_BUS_AHB2: LL_AHB2_GRP1_DisableClock(pclken->enr); break; diff --git a/drivers/clock_control/stm32f2x_ll_clock.c b/drivers/clock_control/stm32f2x_ll_clock.c new file mode 100644 index 00000000000..31499b24a09 --- /dev/null +++ b/drivers/clock_control/stm32f2x_ll_clock.c @@ -0,0 +1,52 @@ +/* + * + * Copyright (c) 2018 qianfan Zhao + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include +#include +#include +#include +#include +#include "stm32_ll_clock.h" + + +#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL + +/* Macros to fill up division factors values */ +#define _pllm(v) LL_RCC_PLLM_DIV_ ## v +#define pllm(v) _pllm(v) + +#define _pllp(v) LL_RCC_PLLP_DIV_ ## v +#define pllp(v) _pllp(v) + +/** + * @brief fill in pll configuration structure + */ +void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit) +{ + pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR); + pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER; + pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR); +} +#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */ + +/** + * @brief Activate default clocks + */ +void config_enable_default_clocks(void) +{ + /* Power Interface clock enabled by default */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); +} + +/** + * @brief Function kept for driver genericity + */ +void LL_RCC_MSI_Disable(void) +{ + /* Do nothing */ +} diff --git a/dts/arm/st/stm32f2.dtsi b/dts/arm/st/stm32f2.dtsi index ea80015d994..37e3c9905b9 100644 --- a/dts/arm/st/stm32f2.dtsi +++ b/dts/arm/st/stm32f2.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { @@ -39,5 +40,13 @@ write-block-size = <1>; }; }; + + rcc: rcc@40023800 { + compatible = "st,stm32-rcc"; + clocks-controller; + #clock-cells = <2>; + reg = <0x40023800 0x400>; + label = "STM32_CLK_RCC"; + }; }; };