michaelh/zephyr
1
0
Fork 0
Code Releases Activity

audio: intel_dmic: get dma properties from devicetree

Browse source 
Move to using devicetree to get dma controller and dma channel
information.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2021-02-26 12:14:09 -06:00 • committed by Anas Nashif
commit 5d02978640
3 changed files with 6 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

9
drivers/audio/intel_dmic.c
View file

@ -22,6 +22,9 @@
#include "intel_dmic.h" #include "intel_dmic.h"
#include "decimation/pdm_decim_fir.h" #include "decimation/pdm_decim_fir.h"
#define DMA_CHANNEL_DMIC_RXA DT_INST_DMAS_CELL_BY_NAME(0, rx_a, channel)
#define DMA_CHANNEL_DMIC_RXB DT_INST_DMAS_CELL_BY_NAME(0, rx_b, channel)
#define LOG_LEVEL CONFIG_AUDIO_DMIC_LOG_LEVEL #define LOG_LEVEL CONFIG_AUDIO_DMIC_LOG_LEVEL
#include <logging/log.h> #include <logging/log.h>
LOG_MODULE_REGISTER(audio_dmic); LOG_MODULE_REGISTER(audio_dmic);
@ -1388,9 +1391,9 @@ int dmic_configure_dma(struct pcm_stream_cfg *config, uint8_t num_streams)
.dma_callback = dmic_dma_callback, .dma_callback = dmic_dma_callback,
}; };
dmic_private.dma_dev = device_get_binding(DMIC_DMA_DEV_NAME); dmic_private.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(0, 0));
if (!dmic_private.dma_dev) { if (!device_is_ready(dmic_private.dma_dev)) {
LOG_ERR("Failed to bind to device: %s", DMIC_DMA_DEV_NAME); LOG_ERR("Failed - device is not ready: %s", dmic_private.dma_dev->name);
return -ENODEV; return -ENODEV;
} }

4
drivers/audio/intel_dmic.h
View file

@ -222,10 +222,6 @@
/* max number of streams supported by hardware 2 = Stream A & B */ /* max number of streams supported by hardware 2 = Stream A & B */
#define DMIC_MAX_STREAMS 2 #define DMIC_MAX_STREAMS 2
#define DMIC_DMA_DEV_NAME CONFIG_DMA_0_NAME
#define DMA_CHANNEL_DMIC_RXA 0
#define DMA_CHANNEL_DMIC_RXB 1
#define DMA_HANDSHAKE_DMIC_RXA 0 #define DMA_HANDSHAKE_DMIC_RXA 0
#define DMA_HANDSHAKE_DMIC_RXB 1 #define DMA_HANDSHAKE_DMIC_RXB 1

8
soc/xtensa/intel_s1000/soc.h
View file

@ -62,14 +62,6 @@
#define DMA_HANDSHAKE_SSP3_TX 8 #define DMA_HANDSHAKE_SSP3_TX 8
#define DMA_HANDSHAKE_SSP3_RX 9 #define DMA_HANDSHAKE_SSP3_RX 9
/* DMA Channel Allocation
* FIXME: I2S Driver assigns channel in Kconfig.
* Perhaps DTS is a better option
*/
#define DMIC_DMA_DEV_NAME CONFIG_DMA_0_NAME
#define DMA_CHANNEL_DMIC_RXA 0
#define DMA_CHANNEL_DMIC_RXB 1
/* I2S */ /* I2S */
#define I2S_CAVS_IRQ(i2s_num) \ #define I2S_CAVS_IRQ(i2s_num) \
SOC_AGGREGATE_IRQ(0, (i2s_num) + 1, CAVS_L2_AGG_INT_LEVEL5) SOC_AGGREGATE_IRQ(0, (i2s_num) + 1, CAVS_L2_AGG_INT_LEVEL5)