boards: esp32s3_devkitm: add appcpu board model

Adds into esp32s3_devkitm the appcpu board to allow
building applications running in ESP32S3 2nd core (appcpu).

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>

boards/xtensa/esp32s3_devkitm/Kconfig.board

@@ -6,6 +6,10 @@ config BOARD_ESP32S3_DEVKITM
 	bool "ESP32S3 DevKitM Board"
 	depends on SOC_SERIES_ESP32S3
 
+config BOARD_ESP32S3_DEVKITM_APPCPU
+	bool "ESP32S3 Board configuration for APPCPU (core 1)."
+	depends on SOC_SERIES_ESP32S3 && SOC_ESP32S3_APPCPU
+
 choice SOC_PART_NUMBER
 	default SOC_ESP32S3_MINI_N8
 endchoice

boards/xtensa/esp32s3_devkitm/Kconfig.defconfig

@@ -3,12 +3,10 @@
 # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
+if BOARD_ESP32S3_DEVKITM
+
 config BOARD
 	default "esp32s3_devkitm"
-	depends on BOARD_ESP32S3_DEVKITM
-
-config ENTROPY_GENERATOR
-	default y
 
 config HEAP_MEM_POOL_SIZE
 	default 98304 if WIFI
@@ -18,3 +16,20 @@ config HEAP_MEM_POOL_SIZE
 choice BT_HCI_BUS_TYPE
 	default BT_ESP32 if BT
 endchoice
+
+endif
+
+if BOARD_ESP32S3_DEVKITM_APPCPU
+
+config BOARD
+	default "esp32s3_devkitm_appcpu"
+
+config HEAP_MEM_POOL_SIZE
+	default 4096
+
+config KERNEL_BIN_NAME
+	default "esp32_net_firmware"
+endif
+
+config ENTROPY_GENERATOR
+	default y

boards/xtensa/esp32s3_devkitm/doc/index.rst

@@ -71,6 +71,13 @@ Security:
 - 4-Kbit OTP, up to 1792 bits for users
 - Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature)
 
+Asymmetric Multiprocessing (AMP)
+********************************
+
+ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core
+architecture, each core can be enabled to execute customized tasks in stand-alone mode
+and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference.
+
 For more information, check the datasheet at `ESP32-S3 Datasheet`_.
 
 Supported Features

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
+/ {
+	model = "esp32s3_appcpu";
+	compatible = "espressif,esp32s3_appcpu";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <ESP32_CLK_CPU_240M>;
+};
+
+&cpu1 {
+	clock-frequency = <ESP32_CLK_CPU_240M>;
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml

@@ -0,0 +1,26 @@
+identifier: esp32s3_devkitm_appcpu
+name: ESP32S3 DEVKITM APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp

boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_ESP32S3=y
+CONFIG_SOC_ESP32S3_APPCPU=y
+CONFIG_BOARD_ESP32S3_DEVKITM_APPCPU=y
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_CLOCK_CONTROL=y
+CONFIG_MINIMAL_LIBC=y