soc: arm: stm32f4: Add Initial MPU Support
This patch adds initial MPU support to STM32F401XE. The boot configuration prevents the following security issues: * Prevent to read at an address that is reserved in the memory map. * Prevent to write into the boot Flash/ROM. * Prevent the application to access to the BootROM. * Prevent from running code located in SRAM. Change-Id: I4dc0669009bd5c0a829a69f8ff417c787b7043ed Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
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@ -13,6 +13,7 @@ config SOC_SERIES_STM32F4X
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select SOC_FAMILY_STM32
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select SYS_POWER_LOW_POWER_STATE_SUPPORTED
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select HAS_STM32CUBE
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select CPU_HAS_MPU
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select CPU_HAS_SYSTICK
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help
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Enable support for STM32F4 MCU series
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@ -22,3 +22,23 @@ config SOC_STM32F429XX
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bool "STM32F429XX"
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endchoice
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config STM32_ARM_MPU_ENABLE
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bool "Enable MPU"
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depends on CPU_HAS_MPU
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select ARM_MPU
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default n
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help
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Enable MPU
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choice
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prompt "Configure Bootloader Options"
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depends on MPU_ENABLE
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config BL_BOOTLOADER
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bool "Build the Bootloader"
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config BL_APPLICATION
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bool "Build an Application"
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endchoice
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@ -2,6 +2,7 @@ obj-y += soc.o
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obj-$(CONFIG_GPIO) += soc_gpio.o
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obj-$(CONFIG_PINMUX) += soc_pinmux.o
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obj-$(CONFIG_STM32_ARM_MPU_ENABLE) += arm_mpu_regions.o
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zephyr: $(KERNEL_HEX_NAME)
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all: $(KERNEL_HEX_NAME)
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70
arch/arm/soc/st_stm32/stm32f4/arm_mpu_mem_cfg.h
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70
arch/arm/soc/st_stm32/stm32f4/arm_mpu_mem_cfg.h
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@ -0,0 +1,70 @@
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARM_MPU_MEM_CFG_H_
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#define _ARM_MPU_MEM_CFG_H_
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#include <soc.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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/* Flash Region Definitions */
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#if CONFIG_FLASH_SIZE == 64
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#define REGION_FLASH_SIZE REGION_64K
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#elif CONFIG_FLASH_SIZE == 128
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#define REGION_FLASH_SIZE REGION_128K
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#elif CONFIG_FLASH_SIZE == 256
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#define REGION_FLASH_SIZE REGION_256K
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#elif CONFIG_FLASH_SIZE == 512
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#define REGION_FLASH_SIZE REGION_512K
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#elif CONFIG_FLASH_SIZE == 1024
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#define REGION_FLASH_SIZE REGION_1024K
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#elif CONFIG_FLASH_SIZE == 2048
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#define REGION_FLASH_SIZE REGION_2048K
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#else
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#error "Unsupported configuration"
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#endif
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/* SRAM Region Definitions */
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#if CONFIG_SRAM_SIZE == 12
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#define REGION_SRAM_0_SIZE REGION_8K
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#define REGION_SRAM_1_START 0x2000
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#define REGION_SRAM_1_SIZE REGION_4K
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#elif CONFIG_SRAM_SIZE == 20
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#define REGION_SRAM_0_SIZE REGION_16K
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#define REGION_SRAM_1_START 0x4000
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#define REGION_SRAM_1_SIZE REGION_4K
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#elif CONFIG_SRAM_SIZE == 32
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#define REGION_SRAM_0_SIZE REGION_16K
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#define REGION_SRAM_1_START 0x4000
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#define REGION_SRAM_1_SIZE REGION_16K
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#elif CONFIG_SRAM_SIZE == 40
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#define REGION_SRAM_0_SIZE REGION_32K
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#define REGION_SRAM_1_START 0x8000
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#define REGION_SRAM_1_SIZE REGION_8K
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#elif CONFIG_SRAM_SIZE == 64
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#define REGION_SRAM_0_SIZE REGION_32K
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#define REGION_SRAM_1_START 0x8000
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#define REGION_SRAM_1_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 96
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#define REGION_SRAM_0_SIZE REGION_64K
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#define REGION_SRAM_1_START 0x10000
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#define REGION_SRAM_1_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 128
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#define REGION_SRAM_0_SIZE REGION_64K
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#define REGION_SRAM_1_START 0x10000
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#define REGION_SRAM_1_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 192
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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#define REGION_SRAM_1_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 256
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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#define REGION_SRAM_1_SIZE REGION_128K
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#else
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#error "Unsupported configuration"
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#endif
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#endif /* _ARM_MPU_MEM_CFG_H_ */
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53
arch/arm/soc/st_stm32/stm32f4/arm_mpu_regions.c
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arch/arm/soc/st_stm32/stm32f4/arm_mpu_regions.c
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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#include "arm_mpu_mem_cfg.h"
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/* SoC Private Peripheral Bus */
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#define PPB_BASE 0xE0000000
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static struct arm_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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/* Region 1 */
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MPU_REGION_ENTRY("RAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
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/* Region 2 */
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MPU_REGION_ENTRY("RAM_1",
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(CONFIG_SRAM_BASE_ADDRESS + REGION_SRAM_1_START),
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REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
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/* Region 3 */
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MPU_REGION_ENTRY("PERIPHERAL_0",
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APB1PERIPH_BASE,
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REGION_IO_ATTR(REGION_512M)),
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/* Region 4 */
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MPU_REGION_ENTRY("PPB_0",
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PPB_BASE,
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REGION_PPB_ATTR(REGION_256M)),
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#if defined(CONFIG_BL_APPLICATION)
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/* Region 5 */
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/*
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* The application booting from a bootloader has no access to the
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* bootloader region. This behavior can be changed at runtime by
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* the bootloader.
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*/
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MPU_REGION_ENTRY("BOOTLOADER_0",
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CONFIG_FLASH_BASE_ADDRESS,
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(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE |
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REGION_32K | P_NA_U_NA)),
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#endif
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};
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struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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