drivers: hwinfo: implemented hardware info support for RT11xx SOC
RT11xx SOC uses same system reset controller as RT10xx series. Add support for SRC on RT11xx Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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9b59721ab3
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6 changed files with 126 additions and 0 deletions
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@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX hwinfo_litex.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM hwinfo_mcux_rcm.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM hwinfo_mcux_rcm.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM hwinfo_mcux_sim.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM hwinfo_mcux_sim.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC hwinfo_mcux_src.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC hwinfo_mcux_src.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 hwinfo_mcux_src_rev2.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SYSCON hwinfo_mcux_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SYSCON hwinfo_mcux_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF hwinfo_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF hwinfo_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6 hwinfo_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6 hwinfo_psoc6.c)
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@ -57,6 +57,13 @@ config HWINFO_MCUX_SRC
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help
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help
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Enable NXP i.MX mcux SRC hwinfo driver.
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Enable NXP i.MX mcux SRC hwinfo driver.
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config HWINFO_MCUX_SRC_V2
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bool "NXP SRC reset cause (multicore devices)"
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default y
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depends on HAS_MCUX_SRC_V2
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help
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Enable version 2 multicore NXP i.MX mcux SRC hwinfo driver.
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config HWINFO_MCUX_SYSCON
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config HWINFO_MCUX_SYSCON
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bool "NXP LPC device ID"
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bool "NXP LPC device ID"
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default y
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default y
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101
drivers/hwinfo/hwinfo_mcux_src_rev2.c
Normal file
101
drivers/hwinfo/hwinfo_mcux_src_rev2.c
Normal file
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@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_src_rev2
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#include <soc.h>
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#include <drivers/hwinfo.h>
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#include <string.h>
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#include <sys/byteorder.h>
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#include <fsl_soc_src.h>
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#ifdef CONFIG_CPU_CORTEX_M7
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#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag
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#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag
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#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag
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#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \
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kSRC_M7CoreWdog3ResetFlag | \
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kSRC_M7CoreWdog4ResetFlag)
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#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag
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#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag
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#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag
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#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag
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#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag
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#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag
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#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \
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kSRC_M4CoreWdog3ResetFlag | \
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kSRC_M4CoreWdog4ResetFlag)
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#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag
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#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag
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#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag
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#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag
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#else
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/* The SOCs currently supported have an M7 or M4 core */
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#error "MCUX SRC driver not supported for this CPU!"
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#endif
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
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if (reason & (MCUX_RESET_PIN_FLAG)) {
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flags |= RESET_PIN;
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}
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if (reason & (MCUX_RESET_SOFTWARE_FLAG)) {
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flags |= RESET_SOFTWARE;
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}
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if (reason & (MCUX_RESET_POR_FLAG)) {
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flags |= RESET_POR;
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}
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if (reason & (MCUX_RESET_WATCHDOG_FLAG)) {
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flags |= RESET_WATCHDOG;
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}
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if (reason & (MCUX_RESET_DEBUG_FLAG)) {
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flags |= RESET_DEBUG;
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}
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if (reason & (MCUX_RESET_SECURITY_FLAG)) {
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flags |= RESET_SECURITY;
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}
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if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) {
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flags |= RESET_TEMPERATURE;
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}
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if (reason & (MCUX_RESET_USER_FLAG)) {
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flags |= RESET_USER;
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}
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
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SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason);
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = (RESET_WATCHDOG
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| RESET_DEBUG
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| RESET_TEMPERATURE
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| RESET_PIN
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| RESET_SOFTWARE
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| RESET_POR
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| RESET_SECURITY
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| RESET_USER
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);
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return 0;
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}
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@ -1043,6 +1043,13 @@
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label = "I2S_3";
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label = "I2S_3";
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};
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};
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src: reset-controller@40c04000 {
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compatible = "nxp,imx-src-rev2";
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reg = <0x40c04000 0x4000>;
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status = "okay";
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label = "SRC";
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};
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};
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};
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};
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};
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@ -207,6 +207,12 @@ config HAS_MCUX_SRC
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Set if the system reset controller (SRC) module is present in the
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Set if the system reset controller (SRC) module is present in the
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SoC.
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SoC.
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config HAS_MCUX_SRC_V2
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bool
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help
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Set if version 2 of the system reset controller (SRC) module is
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present in the SoC.
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config HAS_MCUX_TRNG
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config HAS_MCUX_TRNG
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bool
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bool
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help
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help
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@ -306,6 +306,7 @@ config SOC_MIMXRT1176_CM7
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select HAS_MCUX_GPC
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select HAS_MCUX_GPC
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select HAS_MCUX_I2S
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select HAS_MCUX_I2S
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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config SOC_MIMXRT1176_CM4
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config SOC_MIMXRT1176_CM4
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bool "SOC_MIMXRT1176_CM4"
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bool "SOC_MIMXRT1176_CM4"
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@ -332,6 +333,7 @@ config SOC_MIMXRT1176_CM4
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select HAS_MCUX_ENET
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select HAS_MCUX_ENET
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select HAS_MCUX_GPC
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select HAS_MCUX_GPC
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select HAS_MCUX_I2S
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select HAS_MCUX_I2S
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select HAS_MCUX_SRC_V2
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config SOC_MIMXRT1166_CM7
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config SOC_MIMXRT1166_CM7
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bool "SOC_MIMXRT1166_CM7"
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bool "SOC_MIMXRT1166_CM7"
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@ -366,6 +368,7 @@ config SOC_MIMXRT1166_CM7
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select HAS_MCUX_ENET
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select HAS_MCUX_ENET
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select HAS_MCUX_GPC
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select HAS_MCUX_GPC
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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config SOC_MIMXRT1166_CM4
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config SOC_MIMXRT1166_CM4
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@ -392,6 +395,7 @@ config SOC_MIMXRT1166_CM4
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select HAS_MCUX_USDHC2
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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select HAS_MCUX_ENET
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select HAS_MCUX_GPC
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select HAS_MCUX_GPC
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select HAS_MCUX_SRC_V2
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endchoice
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endchoice
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