From 58a2b1597254911e072e8ba06e1e33dbe21edf77 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 17 Feb 2022 14:49:23 -0600 Subject: [PATCH] drivers: hwinfo: implemented hardware info support for RT11xx SOC RT11xx SOC uses same system reset controller as RT10xx series. Add support for SRC on RT11xx Signed-off-by: Daniel DeGrasse --- drivers/hwinfo/CMakeLists.txt | 1 + drivers/hwinfo/Kconfig | 7 ++ drivers/hwinfo/hwinfo_mcux_src_rev2.c | 101 ++++++++++++++++++++++++++ dts/arm/nxp/nxp_rt11xx.dtsi | 7 ++ modules/Kconfig.mcux | 6 ++ soc/arm/nxp_imx/rt/Kconfig.soc | 4 + 6 files changed, 126 insertions(+) create mode 100644 drivers/hwinfo/hwinfo_mcux_src_rev2.c diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt index f1e29db8ab5..6316722c1c5 100644 --- a/drivers/hwinfo/CMakeLists.txt +++ b/drivers/hwinfo/CMakeLists.txt @@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX hwinfo_litex.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM hwinfo_mcux_rcm.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM hwinfo_mcux_sim.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC hwinfo_mcux_src.c) +zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 hwinfo_mcux_src_rev2.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SYSCON hwinfo_mcux_syscon.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF hwinfo_nrf.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6 hwinfo_psoc6.c) diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index bc1d9f40d0f..39c8438542b 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -57,6 +57,13 @@ config HWINFO_MCUX_SRC help Enable NXP i.MX mcux SRC hwinfo driver. +config HWINFO_MCUX_SRC_V2 + bool "NXP SRC reset cause (multicore devices)" + default y + depends on HAS_MCUX_SRC_V2 + help + Enable version 2 multicore NXP i.MX mcux SRC hwinfo driver. + config HWINFO_MCUX_SYSCON bool "NXP LPC device ID" default y diff --git a/drivers/hwinfo/hwinfo_mcux_src_rev2.c b/drivers/hwinfo/hwinfo_mcux_src_rev2.c new file mode 100644 index 00000000000..431cdfb9f20 --- /dev/null +++ b/drivers/hwinfo/hwinfo_mcux_src_rev2.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_imx_src_rev2 + +#include +#include +#include +#include +#include + +#ifdef CONFIG_CPU_CORTEX_M7 +#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag +#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag +#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag +#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \ + kSRC_M7CoreWdog3ResetFlag | \ + kSRC_M7CoreWdog4ResetFlag) +#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag +#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag +#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag +#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag +#elif defined(CONFIG_CPU_CORTEX_M4) +#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag +#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag +#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag +#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \ + kSRC_M4CoreWdog3ResetFlag | \ + kSRC_M4CoreWdog4ResetFlag) +#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag +#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag +#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag +#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag +#else +/* The SOCs currently supported have an M7 or M4 core */ +#error "MCUX SRC driver not supported for this CPU!" +#endif + +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found"); + +int z_impl_hwinfo_get_reset_cause(uint32_t *cause) +{ + uint32_t flags = 0; + uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0)); + + if (reason & (MCUX_RESET_PIN_FLAG)) { + flags |= RESET_PIN; + } + if (reason & (MCUX_RESET_SOFTWARE_FLAG)) { + flags |= RESET_SOFTWARE; + } + if (reason & (MCUX_RESET_POR_FLAG)) { + flags |= RESET_POR; + } + if (reason & (MCUX_RESET_WATCHDOG_FLAG)) { + flags |= RESET_WATCHDOG; + } + if (reason & (MCUX_RESET_DEBUG_FLAG)) { + flags |= RESET_DEBUG; + } + if (reason & (MCUX_RESET_SECURITY_FLAG)) { + flags |= RESET_SECURITY; + } + if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) { + flags |= RESET_TEMPERATURE; + } + if (reason & (MCUX_RESET_USER_FLAG)) { + flags |= RESET_USER; + } + + *cause = flags; + + return 0; +} + +int z_impl_hwinfo_clear_reset_cause(void) +{ + uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0)); + + SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason); + + return 0; +} + +int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) +{ + *supported = (RESET_WATCHDOG + | RESET_DEBUG + | RESET_TEMPERATURE + | RESET_PIN + | RESET_SOFTWARE + | RESET_POR + | RESET_SECURITY + | RESET_USER + ); + + return 0; +} diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi index c145b7bd8ab..1b5b0f8bcb9 100644 --- a/dts/arm/nxp/nxp_rt11xx.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -1043,6 +1043,13 @@ label = "I2S_3"; }; + src: reset-controller@40c04000 { + compatible = "nxp,imx-src-rev2"; + reg = <0x40c04000 0x4000>; + status = "okay"; + label = "SRC"; + }; + }; }; diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index d547ffdd47e..5f20766a45f 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -207,6 +207,12 @@ config HAS_MCUX_SRC Set if the system reset controller (SRC) module is present in the SoC. +config HAS_MCUX_SRC_V2 + bool + help + Set if version 2 of the system reset controller (SRC) module is + present in the SoC. + config HAS_MCUX_TRNG bool help diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index 712be942155..26872526cb7 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -306,6 +306,7 @@ config SOC_MIMXRT1176_CM7 select HAS_MCUX_GPC select HAS_MCUX_I2S select HAS_MCUX_USB_EHCI + select HAS_MCUX_SRC_V2 config SOC_MIMXRT1176_CM4 bool "SOC_MIMXRT1176_CM4" @@ -332,6 +333,7 @@ config SOC_MIMXRT1176_CM4 select HAS_MCUX_ENET select HAS_MCUX_GPC select HAS_MCUX_I2S + select HAS_MCUX_SRC_V2 config SOC_MIMXRT1166_CM7 bool "SOC_MIMXRT1166_CM7" @@ -366,6 +368,7 @@ config SOC_MIMXRT1166_CM7 select HAS_MCUX_ENET select HAS_MCUX_GPC select HAS_MCUX_USB_EHCI + select HAS_MCUX_SRC_V2 config SOC_MIMXRT1166_CM4 @@ -392,6 +395,7 @@ config SOC_MIMXRT1166_CM4 select HAS_MCUX_USDHC2 select HAS_MCUX_ENET select HAS_MCUX_GPC + select HAS_MCUX_SRC_V2 endchoice