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boards: remove quarl_se_c1000

Browse source 
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2019-07-12 07:54:35 -07:00 • committed by Andrew Boie
commit 578ae40761
130 changed files with 12 additions and 7075 deletions
Download patch file Download diff file Expand all files Collapse all files

8
boards/x86/quark_se_c1000_devboard/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources(
pinmux.c
board.c
)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)

5
boards/x86/quark_se_c1000_devboard/Kconfig.board
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# SPDX-License-Identifier: Apache-2.0
config BOARD_QUARK_SE_C1000_DEVBOARD
bool "Quark SE C1000 Devboard"
depends on SOC_SERIES_QUARK_SE

38
boards/x86/quark_se_c1000_devboard/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
if BOARD_QUARK_SE_C1000_DEVBOARD
config BOARD
default "quark_se_c1000_devboard"
config UART_QMSI_0_HW_FC
default y
if IEEE802154_CC2520
config SPI
default y
config GPIO
default y
config IEEE802154_CC2520_GPIO_SPI_CS
default y
endif # IEEE802154_CC2520
if USB_DEVICE_STACK
config USB_VBUS_GPIO
default y
config USB_VBUS_GPIO_DEV_NAME
default "GPIO_0"
config USB_VBUS_GPIO_PIN_NUM
default 28
endif # USB_DEVICE_STACK
endif # BOARD_QUARK_SE_C1000_DEVBOARD

67
boards/x86/quark_se_c1000_devboard/board.c
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/*
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <drivers/uart.h>
#include <device.h>
#include <init.h>
#if defined(CONFIG_IEEE802154_CC2520)
#include <ieee802154/cc2520.h>
#include <drivers/gpio.h>
static struct cc2520_gpio_configuration cc2520_gpios[CC2520_GPIO_IDX_MAX] = {
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_VREG_EN_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_RESET_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFO_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_CCA_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_SFD_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFOP_GPIOS_PIN, },
};
struct cc2520_gpio_configuration *cc2520_configure_gpios(void)
{
const int flags_noint_out = GPIO_DIR_OUT;
const int flags_noint_in = GPIO_DIR_IN;
const int flags_int_in = (GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
struct device *gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_VREG_EN_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].pin,
flags_noint_out);
cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].dev = gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_RESET_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_RESET].pin,
flags_noint_out);
cc2520_gpios[CC2520_GPIO_IDX_RESET].dev = gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_SFD_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_SFD].pin,
flags_int_in);
cc2520_gpios[CC2520_GPIO_IDX_SFD].dev = gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFOP_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFOP].pin,
flags_int_in);
cc2520_gpios[CC2520_GPIO_IDX_FIFOP].dev = gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFO_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFO].pin,
flags_noint_in);
cc2520_gpios[CC2520_GPIO_IDX_FIFO].dev = gpio;
gpio = device_get_binding(DT_INST_0_TI_CC2520_CCA_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_CCA].pin,
flags_noint_in);
cc2520_gpios[CC2520_GPIO_IDX_CCA].dev = gpio;
return cc2520_gpios;
}
#endif /* CONFIG_IEEE802154_CC2520 */

4
boards/x86/quark_se_c1000_devboard/board.cmake
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# SPDX-License-Identifier: Apache-2.0
board_runner_args(openocd --cmd-pre-load "targets 1")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

107
boards/x86/quark_se_c1000_devboard/doc/index.rst
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.. _quark_se_c1000_devboard:
Quark SE C1000 Development Board
################################
Overview
********
The Intel |reg| Quark |trade| SE microcontroller C1000 is an ultra-low power
Intel Architecture (IA) system-on-chip (SoC) that integrates an Intel |reg|
Quark SE processor core, Sensor subsystem, Memory subsystem (volatile and
non-volatile), pattern matching engine, and industry standard I/O interfaces
into a single silicon-die packaged solution.
Hardware
********
Intel |reg| Quark |trade| SE microcontroller C1000 development platform main expansion
options:
- "Arduino Uno" like SIL sockets (1.8V and 3.3V IO)
- On-board components:
- Certified Bluetooth low energy (BLE) module with integrated antenna
- 802.15.4 transceiver with on-board antenna
- 6-axis Accelerometer / Gyroscope (connected to Sensor subsystem)
- Temperature sensor (connected to Intel® Quark™ SE processor core)
- UART/JTAG to USB converter (USB debug port)
- Other connectors include:
- 2 x USB Device Port – micro Type B
- 5V input a screw terminal/header
- Dual row connectors for all I/O signals from the SoC
- Power sources for this platform:
- External (2.5V - 5V) DC input
- USB power (5V) – via debug / SoC device port
Consult with the `Platform User Guide`_ for more details.
Supported Features
===================
+-----------+------------+-----+-----+-----------------------+
| Interface | Controller | ARC | x86 | Driver/Component |
+===========+============+=====+=====+=======================+
| APIC | on-chip | N | Y | interrupt_controller |
+-----------+------------+-----+-----+-----------------------+
| UART | on-chip | N | Y | serial port-polling; |
| | | | | serial port-interrupt |
+-----------+------------+-----+-----+-----------------------+
| SPI | on-chip | Y | Y | spi |
+-----------+------------+-----+-----+-----------------------+
| ADC | on-chip | Y | N | adc |
+-----------+------------+-----+-----+-----------------------+
| I2C | on-chip | Y | Y | i2c |
+-----------+------------+-----+-----+-----------------------+
| GPIO | on-chip | Y | Y | gpio |
+-----------+------------+-----+-----+-----------------------+
| PWM | on-chip | Y | Y | pwm |
+-----------+------------+-----+-----+-----------------------+
| mailbox | on-chip | Y | Y | ipm |
+-----------+------------+-----+-----+-----------------------+
Programming and Debugging
*************************
The board configuration details are found in the project's tree at
:zephyr_file:`boards/x86/quark_se_c1000_devboard`.
Applications for the ``quark_se_c1000_devboard`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
#. Since the board has a built-in JTAG; it is possible to flash the device
through the USB only.
#. Connect the board via USB to the host computer.
#. Build and flash a Zephyr application. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: quark_se_c1000_devboard
:goals: build flash
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: quark_se_c1000_devboard
:maybe-skip-config:
:goals: debug
.. _Platform User Guide:
https://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-c1000-development-platform-user-guide.pdf

152
boards/x86/quark_se_c1000_devboard/pinmux.c
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/* pinmux_board_quark_se_dev.c - Quark SE Development Board pinmux driver */
/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <soc.h>
#include <device.h>
#include <init.h>
#include <drivers/pinmux.h>
#include <sys/sys_io.h>
#include "pinmux/pinmux.h"
#include <pinmux_quark_mcu.h>
/*
* This is the full pinmap that we have available on the board for configuration
* including the ball position and the various modes that can be set. In the
* pinmux_defaults we do not spend any time setting values that are using mode
* A as the hardware brings up all devices by default in mode A.
*/
/* pin, ball, mode A, mode B, mode C */
/* 0 F02, gpio_0, ain_0, spi_s_cs */
/* 1 G04, gpio_1, ain_1, spi_s_miso */
/* 2 H05, gpio_2, ain_2, spi_s_sck */
/* 3 J06, gpio_3, ain_3, spi_s_mosi */
/* 4 K06, gpio_4, ain_4, NA */ /* 15.4 GPIO */
/* 5 L06, gpio_5, ain_5, NA */ /* 15.4 GPIO */
/* 6 H04, gpio_6, ain_6, NA */ /* 15.4 GPIO */
/* 7 G03, gpio_7, ain_7, NA */
/* 8 L05, gpio_ss_0, ain_8, uart1_cts */ /* UART debug */
/* 9 M05, gpio_ss_1, ain_9, uart1_rts */ /* UART debug */
/* 10 K05, gpio_ss_2, ain_10 */
/* 11 G01, gpio_ss_3, ain_11 */
/* 12 J04, gpio_ss_4, ain_12 */
/* 13 G02, gpio_ss_5, ain_13 */
/* 14 F01, gpio_ss_6, ain_14 */
/* 15 J05, gpio_ss_7, ain_15 */
/* 16 L04, gpio_ss_8, ain_16, uart1_txd */ /* UART debug */
/* 17 M04, gpio_ss_9, ain_17, uart1_rxd */ /* UART debug */
/* 18 K04, uart0_rx, ain_18, NA */ /* BT UART */
/* 19 B02, uart0_tx, gpio_31, NA */ /* BT UART */
/* 20 C01, i2c0_scl, NA, NA */ /* EEPROM, BT, Light Sensor */
/* 21 C02, i2c0_sda, NA, NA */ /* EEPROM, BT, Light Sensor */
/* 22 D01, i2c1_scl, NA, NA */
/* 23 D02, i2c1_sda, NA, NA */
/* 24 E01, i2c0_ss_sda, NA, NA */
/* 25 E02, i2c0_ss_scl, NA, NA */
/* 26 B03, i2c1_ss_sda, NA, NA */ /* IMU */
/* 27 A03, i2c1_ss_scl, NA, NA */ /* IMU */
/* 28 C03, spi0_ss_miso, NA, NA */ /* IMU */
/* 29 E03, spi0_ss_mosi, NA, NA */ /* IMU */
/* 30 D03, spi0_ss_sck, NA, NA */ /* IMU */
/* 31 D04, spi0_ss_cs0, NA, NA */ /* IMU */
/* 32 C04, spi0_ss_cs1, NA, NA */
/* 33 B04, spi0_ss_cs2, gpio_29, NA */ /* 15.4 GPIO */
/* 34 A04, spi0_ss_cs3, gpio_30, NA */
/* 35 B05, spi1_ss_miso, NA, NA */
/* 36 C05, spi1_ss_mosi, NA, NA */
/* 37 D05, spi1_ss_sck, NA, NA */
/* 38 E05, spi1_ss_cs0, NA, NA */
/* 39 E04, spi1_ss_cs1, NA, NA */
/* 40 A06, spi1_ss_cs2, uart0_cts, NA */ /* BT UART */
/* 41 B06, spi1_ss_cs3, uart0_rts, NA */ /* BT UART */
/* 42 C06, gpio_8, spi1_m_sck, NA */ /* 15.4 SPI */
/* 43 D06, gpio_9, spi1_m_miso, NA */ /* 15.4 SPI */
/* 44 E06, gpio_10, spi1_m_mosi, NA */ /* 15.4 SPI */
/* 45 D07, gpio_11, spi1_m_cs0, NA */ /* 15.4 SPI GPIO CS */
/* 46 C07, gpio_12, spi1_m_cs1, NA */
/* 47 B07, gpio_13, spi1_m_cs2, NA */
/* 48 A07, gpio_14, spi1_m_cs3, NA */
/* 49 B08, gpio_15, i2s_rxd, NA */
/* 50 A08, gpio_16, i2s_rscki, NA */
/* 51 B09, gpio_17, i2s_rws, NA */
/* 52 A09, gpio_18, i2s_tsck, NA */
/* 53 C09, gpio_19, i2s_twsi, NA */
/* 54 D09, gpio_20, i2s_txd, NA */
/* 55 D08, gpio_21, spi0_m_sck, NA */ /* SPI Flash */
/* 56 E07, gpio_22, spi0_m_miso, NA */ /* SPI Flash */
/* 57 E09, gpio_23, spi0_m_mosi, NA */ /* SPI Flash */
/* 58 E08, gpio_24, spi0_m_cs0, NA */ /* SPI Flash */
/* 59 A10, gpio_25, spi0_m_cs1, NA */
/* 60 B10, gpio_26, spi0_m_cs2, NA */
/* 61 C10, gpio_27, spi0_m_cs3, NA */
/* 62 D10, gpio_28, NA, NA */
/* 63 E10, gpio_ss_10, pwm_0, NA */
/* 64 D11, gpio_ss_11, pwm_1, NA */
/* 65 C11, gpio_ss_12, pwm_2, NA */
/* 66 B11, gpio_ss_13, pwm_3, NA */
/* 67 D12, gpio_ss_14, clkout_32khz, NA */
/* 68 C12, gpio_ss_15, clkout_16mhz, NA */
/*
* On the QUARK_SE platform there are a minimum of 69 pins that can be possibly
* set. This would be a total of 5 registers to store the configuration as per
* the bit description from above
*/
#define PINMUX_MAX_REGISTERS 5
static void pinmux_defaults(u32_t base)
{
u32_t mux_config[PINMUX_MAX_REGISTERS] = { 0, 0, 0, 0, 0};
int i = 0;
#if defined(CONFIG_SPI_2)
PIN_CONFIG(mux_config, 0, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 1, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 2, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 3, PINMUX_FUNC_C);
#else
PIN_CONFIG(mux_config, 0, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 1, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 2, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 3, PINMUX_FUNC_B);
#endif
PIN_CONFIG(mux_config, 8, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 9, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 16, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 17, PINMUX_FUNC_C);
PIN_CONFIG(mux_config, 33, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 40, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 41, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 42, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 43, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 44, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 55, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 56, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 57, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 58, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 63, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 64, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 65, PINMUX_FUNC_B);
PIN_CONFIG(mux_config, 66, PINMUX_FUNC_B);
for (i = 0; i < PINMUX_MAX_REGISTERS; i++) {
sys_write32(mux_config[i], PINMUX_SELECT_REGISTER(base, i));
}
}
static int pinmux_initialize(struct device *port)
{
ARG_UNUSED(port);
pinmux_defaults(PINMUX_BASE_ADDR);
return 0;
}
SYS_INIT(pinmux_initialize, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

99
boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts
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/* SPDX-License-Identifier: Apache-2.0 */
/dts-v1/;
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(144)
#define DT_SRAM_SIZE DT_SIZE_K(52)
#include "intel_curie.dtsi"
/ {
model = "quark_se_c1000_devboard";
compatible = "intel,quark_se_c1000_devboard", "intel,quark_se_c1000";
aliases {
led0 = &led0;
sw0 = &button0;
sw1 = &button1;
uart-0 = &uart0;
uart-1 = &uart1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash1;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,bt-uart = &uart0;
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 25 0>;
label = "LED";
};
};
buttons {
/* Push button switch 0 KEY1 */
compatible = "gpio-keys";
button0: button_0 {
/* gpio flags need validation */
gpios = <&gpio1 4 GPIO_INT_ACTIVE_LOW>;
label = "Push button switch 0";
};
button1: button_1 {
/* gpio flags need validation */
gpios = <&gpio0 5 GPIO_INT_ACTIVE_LOW>;
label = "Push button switch 1";
};
};
};
&uart0 {
status = "okay";
current-speed = <1000000>;
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c1 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
cs-gpios = <&gpio0 11 0>;
cc2520@0 {
compatible = "ti,cc2520";
reg = <0x0>;
label = "cc2520";
spi-max-frequency = <8000000>;
status = "okay";
vreg-en-gpios = <&gpio1 0 0>;
reset-gpios = <&gpio1 1 0>;
fifo-gpios = <&gpio0 4 0>;
cca-gpios = <&gpio0 6 0>;
sfd-gpios = <&gpio0 29 0>;
fifop-gpios = <&gpio0 5 0>;
};
};

20
boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.yaml
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identifier: quark_se_c1000_devboard
name: Quark SE C1000 Devboard
type: mcu
arch: x86
toolchain:
- zephyr
- issm
- xtools
supported:
- ieee802154
- usb_device
- i2c
- spi
- gpio
- counter
- aio
- watchdog
- dma
ram: 52
flash: 144

15
boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard_defconfig
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# SPDX-License-Identifier: Apache-2.0
CONFIG_X86=y
CONFIG_SOC_QUARK_SE_C1000=y
CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD=y
CONFIG_SOC_SERIES_QUARK_SE=y
CONFIG_SOC_FAMILY_QUARK=y
CONFIG_CPU_MINUTEIA=y
CONFIG_SET_GDT=n
CONFIG_CONSOLE=y
CONFIG_UART_QMSI=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_PRINTK=y
CONFIG_PINMUX=y

8
boards/x86/quark_se_c1000_devboard/support/openocd.cfg
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interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x0010 0xffff
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
source [find board/quark_se.cfg]