diff --git a/CODEOWNERS b/CODEOWNERS index 9456a950970..a3e4e364e0b 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -48,11 +48,9 @@ /arch/x86/core/pcie.c @gnuless /arch/x86/core/multiboot.c @gnuless /soc/x86/ @andrewboie @gnuless -/soc/x86/intel_quark/quark_se/ @nashif /arch/xtensa/ @andrewboie @dcpleung @andyross /soc/xtensa/ @andrewboie @dcpleung @andyross /boards/arc/ @vonhust @ruuddw -/boards/arc/quark_se_c1000_ss_devboard/ @nashif /boards/arm/ @MaureenHelm @galak /boards/arm/96b_argonkey/ @avisconti /boards/arm/96b_avenger96/ @Mani-Sadhasivam diff --git a/boards/arc/quark_se_c1000_ss_devboard/Kconfig.board b/boards/arc/quark_se_c1000_ss_devboard/Kconfig.board deleted file mode 100644 index d1a90e4d665..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QUARK_SE_C1000_DEVBOARD_SS - bool "Quark SE C1000 - Sensor Sub System" - depends on SOC_QUARK_SE_C1000_SS diff --git a/boards/arc/quark_se_c1000_ss_devboard/Kconfig.defconfig b/boards/arc/quark_se_c1000_ss_devboard/Kconfig.defconfig deleted file mode 100644 index dcd79333070..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QUARK_SE_C1000_DEVBOARD_SS - -config BOARD - default "quark_se_c1000_ss_devboard" - -endif # BOARD_QUARK_SE_C1000_DEVBOARD_SS diff --git a/boards/arc/quark_se_c1000_ss_devboard/board.cmake b/boards/arc/quark_se_c1000_ss_devboard/board.cmake deleted file mode 100644 index f0d86376cab..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd --cmd-pre-load "targets 1") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts b/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts deleted file mode 100644 index 05598212bdb..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -#define DT_FLASH_SIZE DT_SIZE_K(152) -#define DT_SRAM_SIZE DT_SIZE_K(24) -#define DT_DCCM_SIZE DT_SIZE_K(8) - -#define DT_FLASH_ADDR 0x40000000 - -#include "quark_se_c1000_ss.dtsi" - -/ { - model = "quark_se_c1000_ss_devboard"; - compatible = "intel,quark_se_c1000_ss_devboard", "intel,quark_se_c1000"; - - aliases { - led0 = &led0; - sw0 = &button0; - sw1 = &button1; - uart-0 = &uart0; - uart-1 = &uart1; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 25 0>; - label = "LED"; - }; - }; - - buttons { - /* Push button switch 0 KEY1 */ - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpio1 4 GPIO_INT_ACTIVE_LOW>; - label = "Push button switch 0"; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpio0 5 GPIO_INT_ACTIVE_LOW>; - label = "Push button switch 1"; - }; - }; - -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; diff --git a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.yaml b/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.yaml deleted file mode 100644 index 10d50cb1055..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: quark_se_c1000_ss_devboard -name: Quark SE C1000 Devboard - Sensor Subsystem -type: mcu -arch: arc -ram: 24 -flash: 152 -toolchain: - - zephyr - - xtools -supported: - - adc - - i2c - - spi - - gpio - - counter - - watchdog -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard_defconfig b/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard_defconfig deleted file mode 100644 index 82ee4970d02..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARC=y -CONFIG_SOC_QUARK_SE_C1000_SS=y -CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000 -CONFIG_XIP=y -CONFIG_PRINTK=y -CONFIG_CPU_ARCEM=y -CONFIG_CPU_ARCV2=y -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_QMSI=y -CONFIG_SERIAL=y diff --git a/boards/arc/quark_se_c1000_ss_devboard/support/openocd.cfg b/boards/arc/quark_se_c1000_ss_devboard/support/openocd.cfg deleted file mode 100644 index 3df06027f22..00000000000 --- a/boards/arc/quark_se_c1000_ss_devboard/support/openocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ - -interface ftdi -ftdi_vid_pid 0x0403 0x6010 - -ftdi_channel 0 -ftdi_layout_init 0x0010 0xffff -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 - -source [find board/quark_se.cfg] diff --git a/boards/arm/quark_se_c1000_ble/Kconfig.board b/boards/arm/quark_se_c1000_ble/Kconfig.board deleted file mode 100644 index db947ad9402..00000000000 --- a/boards/arm/quark_se_c1000_ble/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Kconfig - Quark SE C1000 BLE (nRF51822) configuration -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QUARK_SE_C1000_BLE - bool "Quark SE C1000 Devboard - BLE Core" - depends on SOC_NRF51822_QFAA diff --git a/boards/arm/quark_se_c1000_ble/Kconfig.defconfig b/boards/arm/quark_se_c1000_ble/Kconfig.defconfig deleted file mode 100644 index f75969e1442..00000000000 --- a/boards/arm/quark_se_c1000_ble/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Kconfig - Quark SE C1000 BLE (nRF51822) configuration -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QUARK_SE_C1000_BLE - -config BOARD - default "quark_se_c1000_ble" - -config BT_CTLR - default BT - -endif # BOARD_QUARK_SE_C1000_BLE diff --git a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.dts b/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.dts deleted file mode 100644 index d52c80f7259..00000000000 --- a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include - -/ { - model = "Intel Quark SE C1000 BLE"; - compatible = "intel,quark-se-c1000-ble", "nordic,nrf51822-qfaa", - "nordic,nrf51822"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <1000000>; - tx-pin = <9>; - rx-pin = <11>; - rts-pin = <8>; - cts-pin = <10>; -}; diff --git a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.yaml b/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.yaml deleted file mode 100644 index 42bee309471..00000000000 --- a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: quark_se_c1000_ble -name: Quark SE C1000 Devboard (nRF51) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 16 -supported: - - ble -testing: - ignore_tags: - - net diff --git a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig b/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig deleted file mode 100644 index f921c301b34..00000000000 --- a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM=y -CONFIG_SOC_FAMILY_NRF=y -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_QUARK_SE_C1000_BLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y -CONFIG_UART_0_NRF_UART=y diff --git a/boards/x86/quark_se_c1000_devboard/CMakeLists.txt b/boards/x86/quark_se_c1000_devboard/CMakeLists.txt deleted file mode 100644 index 836442f96cf..00000000000 --- a/boards/x86/quark_se_c1000_devboard/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources( - pinmux.c - board.c - ) -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) diff --git a/boards/x86/quark_se_c1000_devboard/Kconfig.board b/boards/x86/quark_se_c1000_devboard/Kconfig.board deleted file mode 100644 index d2b10a8b7d1..00000000000 --- a/boards/x86/quark_se_c1000_devboard/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QUARK_SE_C1000_DEVBOARD - bool "Quark SE C1000 Devboard" - depends on SOC_SERIES_QUARK_SE diff --git a/boards/x86/quark_se_c1000_devboard/Kconfig.defconfig b/boards/x86/quark_se_c1000_devboard/Kconfig.defconfig deleted file mode 100644 index d8dfbfcc517..00000000000 --- a/boards/x86/quark_se_c1000_devboard/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QUARK_SE_C1000_DEVBOARD - -config BOARD - default "quark_se_c1000_devboard" - - -config UART_QMSI_0_HW_FC - default y - -if IEEE802154_CC2520 - -config SPI - default y - -config GPIO - default y - -config IEEE802154_CC2520_GPIO_SPI_CS - default y - -endif # IEEE802154_CC2520 - -if USB_DEVICE_STACK - -config USB_VBUS_GPIO - default y - -config USB_VBUS_GPIO_DEV_NAME - default "GPIO_0" - -config USB_VBUS_GPIO_PIN_NUM - default 28 - -endif # USB_DEVICE_STACK - -endif # BOARD_QUARK_SE_C1000_DEVBOARD diff --git a/boards/x86/quark_se_c1000_devboard/board.c b/boards/x86/quark_se_c1000_devboard/board.c deleted file mode 100644 index 0bc370f5f8c..00000000000 --- a/boards/x86/quark_se_c1000_devboard/board.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#if defined(CONFIG_IEEE802154_CC2520) - -#include -#include - -static struct cc2520_gpio_configuration cc2520_gpios[CC2520_GPIO_IDX_MAX] = { - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_VREG_EN_GPIOS_PIN, }, - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_RESET_GPIOS_PIN, }, - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFO_GPIOS_PIN, }, - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_CCA_GPIOS_PIN, }, - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_SFD_GPIOS_PIN, }, - { .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFOP_GPIOS_PIN, }, -}; - -struct cc2520_gpio_configuration *cc2520_configure_gpios(void) -{ - const int flags_noint_out = GPIO_DIR_OUT; - const int flags_noint_in = GPIO_DIR_IN; - const int flags_int_in = (GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | - GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE); - struct device *gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_VREG_EN_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].pin, - flags_noint_out); - cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].dev = gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_RESET_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_RESET].pin, - flags_noint_out); - cc2520_gpios[CC2520_GPIO_IDX_RESET].dev = gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_SFD_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_SFD].pin, - flags_int_in); - cc2520_gpios[CC2520_GPIO_IDX_SFD].dev = gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFOP_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFOP].pin, - flags_int_in); - cc2520_gpios[CC2520_GPIO_IDX_FIFOP].dev = gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFO_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFO].pin, - flags_noint_in); - cc2520_gpios[CC2520_GPIO_IDX_FIFO].dev = gpio; - - gpio = device_get_binding(DT_INST_0_TI_CC2520_CCA_GPIOS_CONTROLLER); - gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_CCA].pin, - flags_noint_in); - cc2520_gpios[CC2520_GPIO_IDX_CCA].dev = gpio; - - return cc2520_gpios; -} - -#endif /* CONFIG_IEEE802154_CC2520 */ diff --git a/boards/x86/quark_se_c1000_devboard/board.cmake b/boards/x86/quark_se_c1000_devboard/board.cmake deleted file mode 100644 index f0d86376cab..00000000000 --- a/boards/x86/quark_se_c1000_devboard/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd --cmd-pre-load "targets 1") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/x86/quark_se_c1000_devboard/doc/index.rst b/boards/x86/quark_se_c1000_devboard/doc/index.rst deleted file mode 100644 index 5d633934d1f..00000000000 --- a/boards/x86/quark_se_c1000_devboard/doc/index.rst +++ /dev/null @@ -1,107 +0,0 @@ -.. _quark_se_c1000_devboard: - -Quark SE C1000 Development Board -################################ - -Overview -******** - -The Intel |reg| Quark |trade| SE microcontroller C1000 is an ultra-low power -Intel Architecture (IA) system-on-chip (SoC) that integrates an Intel |reg| -Quark SE processor core, Sensor subsystem, Memory subsystem (volatile and -non-volatile), pattern matching engine, and industry standard I/O interfaces -into a single silicon-die packaged solution. - -Hardware -******** - -Intel |reg| Quark |trade| SE microcontroller C1000 development platform main expansion -options: - -- "Arduino Uno" like SIL sockets (1.8V and 3.3V IO) -- On-board components: - - - Certified Bluetooth low energy (BLE) module with integrated antenna - - 802.15.4 transceiver with on-board antenna - - 6-axis Accelerometer / Gyroscope (connected to Sensor subsystem) - - Temperature sensor (connected to Intel® Quark™ SE processor core) - - UART/JTAG to USB converter (USB debug port) -- Other connectors include: - - - 2 x USB Device Port – micro Type B - - 5V input a screw terminal/header - - Dual row connectors for all I/O signals from the SoC - -- Power sources for this platform: - - - External (2.5V - 5V) DC input - - USB power (5V) – via debug / SoC device port - - -Consult with the `Platform User Guide`_ for more details. - -Supported Features -=================== - - -+-----------+------------+-----+-----+-----------------------+ -| Interface | Controller | ARC | x86 | Driver/Component | -+===========+============+=====+=====+=======================+ -| APIC | on-chip | N | Y | interrupt_controller | -+-----------+------------+-----+-----+-----------------------+ -| UART | on-chip | N | Y | serial port-polling; | -| | | | | serial port-interrupt | -+-----------+------------+-----+-----+-----------------------+ -| SPI | on-chip | Y | Y | spi | -+-----------+------------+-----+-----+-----------------------+ -| ADC | on-chip | Y | N | adc | -+-----------+------------+-----+-----+-----------------------+ -| I2C | on-chip | Y | Y | i2c | -+-----------+------------+-----+-----+-----------------------+ -| GPIO | on-chip | Y | Y | gpio | -+-----------+------------+-----+-----+-----------------------+ -| PWM | on-chip | Y | Y | pwm | -+-----------+------------+-----+-----+-----------------------+ -| mailbox | on-chip | Y | Y | ipm | -+-----------+------------+-----+-----+-----------------------+ - -Programming and Debugging -************************* - -The board configuration details are found in the project's tree at -:zephyr_file:`boards/x86/quark_se_c1000_devboard`. - -Applications for the ``quark_se_c1000_devboard`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -#. Since the board has a built-in JTAG; it is possible to flash the device - through the USB only. - -#. Connect the board via USB to the host computer. - -#. Build and flash a Zephyr application. Here is an example for the - :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: quark_se_c1000_devboard - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: quark_se_c1000_devboard - :maybe-skip-config: - :goals: debug - -.. _Platform User Guide: - https://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-c1000-development-platform-user-guide.pdf diff --git a/boards/x86/quark_se_c1000_devboard/pinmux.c b/boards/x86/quark_se_c1000_devboard/pinmux.c deleted file mode 100644 index f518f132444..00000000000 --- a/boards/x86/quark_se_c1000_devboard/pinmux.c +++ /dev/null @@ -1,152 +0,0 @@ -/* pinmux_board_quark_se_dev.c - Quark SE Development Board pinmux driver */ - -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include "pinmux/pinmux.h" - -#include - -/* - * This is the full pinmap that we have available on the board for configuration - * including the ball position and the various modes that can be set. In the - * pinmux_defaults we do not spend any time setting values that are using mode - * A as the hardware brings up all devices by default in mode A. - */ - -/* pin, ball, mode A, mode B, mode C */ -/* 0 F02, gpio_0, ain_0, spi_s_cs */ -/* 1 G04, gpio_1, ain_1, spi_s_miso */ -/* 2 H05, gpio_2, ain_2, spi_s_sck */ -/* 3 J06, gpio_3, ain_3, spi_s_mosi */ -/* 4 K06, gpio_4, ain_4, NA */ /* 15.4 GPIO */ -/* 5 L06, gpio_5, ain_5, NA */ /* 15.4 GPIO */ -/* 6 H04, gpio_6, ain_6, NA */ /* 15.4 GPIO */ -/* 7 G03, gpio_7, ain_7, NA */ -/* 8 L05, gpio_ss_0, ain_8, uart1_cts */ /* UART debug */ -/* 9 M05, gpio_ss_1, ain_9, uart1_rts */ /* UART debug */ -/* 10 K05, gpio_ss_2, ain_10 */ -/* 11 G01, gpio_ss_3, ain_11 */ -/* 12 J04, gpio_ss_4, ain_12 */ -/* 13 G02, gpio_ss_5, ain_13 */ -/* 14 F01, gpio_ss_6, ain_14 */ -/* 15 J05, gpio_ss_7, ain_15 */ -/* 16 L04, gpio_ss_8, ain_16, uart1_txd */ /* UART debug */ -/* 17 M04, gpio_ss_9, ain_17, uart1_rxd */ /* UART debug */ -/* 18 K04, uart0_rx, ain_18, NA */ /* BT UART */ -/* 19 B02, uart0_tx, gpio_31, NA */ /* BT UART */ -/* 20 C01, i2c0_scl, NA, NA */ /* EEPROM, BT, Light Sensor */ -/* 21 C02, i2c0_sda, NA, NA */ /* EEPROM, BT, Light Sensor */ -/* 22 D01, i2c1_scl, NA, NA */ -/* 23 D02, i2c1_sda, NA, NA */ -/* 24 E01, i2c0_ss_sda, NA, NA */ -/* 25 E02, i2c0_ss_scl, NA, NA */ -/* 26 B03, i2c1_ss_sda, NA, NA */ /* IMU */ -/* 27 A03, i2c1_ss_scl, NA, NA */ /* IMU */ -/* 28 C03, spi0_ss_miso, NA, NA */ /* IMU */ -/* 29 E03, spi0_ss_mosi, NA, NA */ /* IMU */ -/* 30 D03, spi0_ss_sck, NA, NA */ /* IMU */ -/* 31 D04, spi0_ss_cs0, NA, NA */ /* IMU */ -/* 32 C04, spi0_ss_cs1, NA, NA */ -/* 33 B04, spi0_ss_cs2, gpio_29, NA */ /* 15.4 GPIO */ -/* 34 A04, spi0_ss_cs3, gpio_30, NA */ -/* 35 B05, spi1_ss_miso, NA, NA */ -/* 36 C05, spi1_ss_mosi, NA, NA */ -/* 37 D05, spi1_ss_sck, NA, NA */ -/* 38 E05, spi1_ss_cs0, NA, NA */ -/* 39 E04, spi1_ss_cs1, NA, NA */ -/* 40 A06, spi1_ss_cs2, uart0_cts, NA */ /* BT UART */ -/* 41 B06, spi1_ss_cs3, uart0_rts, NA */ /* BT UART */ -/* 42 C06, gpio_8, spi1_m_sck, NA */ /* 15.4 SPI */ -/* 43 D06, gpio_9, spi1_m_miso, NA */ /* 15.4 SPI */ -/* 44 E06, gpio_10, spi1_m_mosi, NA */ /* 15.4 SPI */ -/* 45 D07, gpio_11, spi1_m_cs0, NA */ /* 15.4 SPI GPIO CS */ -/* 46 C07, gpio_12, spi1_m_cs1, NA */ -/* 47 B07, gpio_13, spi1_m_cs2, NA */ -/* 48 A07, gpio_14, spi1_m_cs3, NA */ -/* 49 B08, gpio_15, i2s_rxd, NA */ -/* 50 A08, gpio_16, i2s_rscki, NA */ -/* 51 B09, gpio_17, i2s_rws, NA */ -/* 52 A09, gpio_18, i2s_tsck, NA */ -/* 53 C09, gpio_19, i2s_twsi, NA */ -/* 54 D09, gpio_20, i2s_txd, NA */ -/* 55 D08, gpio_21, spi0_m_sck, NA */ /* SPI Flash */ -/* 56 E07, gpio_22, spi0_m_miso, NA */ /* SPI Flash */ -/* 57 E09, gpio_23, spi0_m_mosi, NA */ /* SPI Flash */ -/* 58 E08, gpio_24, spi0_m_cs0, NA */ /* SPI Flash */ -/* 59 A10, gpio_25, spi0_m_cs1, NA */ -/* 60 B10, gpio_26, spi0_m_cs2, NA */ -/* 61 C10, gpio_27, spi0_m_cs3, NA */ -/* 62 D10, gpio_28, NA, NA */ -/* 63 E10, gpio_ss_10, pwm_0, NA */ -/* 64 D11, gpio_ss_11, pwm_1, NA */ -/* 65 C11, gpio_ss_12, pwm_2, NA */ -/* 66 B11, gpio_ss_13, pwm_3, NA */ -/* 67 D12, gpio_ss_14, clkout_32khz, NA */ -/* 68 C12, gpio_ss_15, clkout_16mhz, NA */ - -/* - * On the QUARK_SE platform there are a minimum of 69 pins that can be possibly - * set. This would be a total of 5 registers to store the configuration as per - * the bit description from above - */ -#define PINMUX_MAX_REGISTERS 5 -static void pinmux_defaults(u32_t base) -{ - u32_t mux_config[PINMUX_MAX_REGISTERS] = { 0, 0, 0, 0, 0}; - int i = 0; - -#if defined(CONFIG_SPI_2) - PIN_CONFIG(mux_config, 0, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 1, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 2, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 3, PINMUX_FUNC_C); -#else - PIN_CONFIG(mux_config, 0, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 1, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 2, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 3, PINMUX_FUNC_B); -#endif - PIN_CONFIG(mux_config, 8, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 9, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 16, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 17, PINMUX_FUNC_C); - PIN_CONFIG(mux_config, 33, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 40, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 41, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 42, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 43, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 44, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 55, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 56, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 57, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 58, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 63, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 64, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 65, PINMUX_FUNC_B); - PIN_CONFIG(mux_config, 66, PINMUX_FUNC_B); - - for (i = 0; i < PINMUX_MAX_REGISTERS; i++) { - sys_write32(mux_config[i], PINMUX_SELECT_REGISTER(base, i)); - } -} - -static int pinmux_initialize(struct device *port) -{ - ARG_UNUSED(port); - - pinmux_defaults(PINMUX_BASE_ADDR); - - return 0; -} - -SYS_INIT(pinmux_initialize, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts b/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts deleted file mode 100644 index 88994cd8112..00000000000 --- a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -#define DT_FLASH_SIZE DT_SIZE_K(144) -#define DT_SRAM_SIZE DT_SIZE_K(52) - -#include "intel_curie.dtsi" - -/ { - model = "quark_se_c1000_devboard"; - compatible = "intel,quark_se_c1000_devboard", "intel,quark_se_c1000"; - - aliases { - led0 = &led0; - sw0 = &button0; - sw1 = &button1; - uart-0 = &uart0; - uart-1 = &uart1; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash1; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,bt-uart = &uart0; - zephyr,uart-pipe = &uart1; - zephyr,bt-mon-uart = &uart1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 25 0>; - label = "LED"; - }; - }; - - buttons { - /* Push button switch 0 KEY1 */ - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpio1 4 GPIO_INT_ACTIVE_LOW>; - label = "Push button switch 0"; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpio0 5 GPIO_INT_ACTIVE_LOW>; - label = "Push button switch 1"; - }; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <1000000>; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; -}; - -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - cs-gpios = <&gpio0 11 0>; - - cc2520@0 { - compatible = "ti,cc2520"; - reg = <0x0>; - label = "cc2520"; - spi-max-frequency = <8000000>; - status = "okay"; - vreg-en-gpios = <&gpio1 0 0>; - reset-gpios = <&gpio1 1 0>; - fifo-gpios = <&gpio0 4 0>; - cca-gpios = <&gpio0 6 0>; - sfd-gpios = <&gpio0 29 0>; - fifop-gpios = <&gpio0 5 0>; - }; -}; diff --git a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.yaml b/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.yaml deleted file mode 100644 index bbc7317be23..00000000000 --- a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: quark_se_c1000_devboard -name: Quark SE C1000 Devboard -type: mcu -arch: x86 -toolchain: - - zephyr - - issm - - xtools -supported: - - ieee802154 - - usb_device - - i2c - - spi - - gpio - - counter - - aio - - watchdog - - dma -ram: 52 -flash: 144 diff --git a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard_defconfig b/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard_defconfig deleted file mode 100644 index 8a17fa70b2b..00000000000 --- a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_X86=y -CONFIG_SOC_QUARK_SE_C1000=y -CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD=y -CONFIG_SOC_SERIES_QUARK_SE=y -CONFIG_SOC_FAMILY_QUARK=y -CONFIG_CPU_MINUTEIA=y -CONFIG_SET_GDT=n -CONFIG_CONSOLE=y -CONFIG_UART_QMSI=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_PRINTK=y -CONFIG_PINMUX=y diff --git a/boards/x86/quark_se_c1000_devboard/support/openocd.cfg b/boards/x86/quark_se_c1000_devboard/support/openocd.cfg deleted file mode 100644 index 77d33026c87..00000000000 --- a/boards/x86/quark_se_c1000_devboard/support/openocd.cfg +++ /dev/null @@ -1,8 +0,0 @@ -interface ftdi -ftdi_vid_pid 0x0403 0x6010 - -ftdi_channel 0 -ftdi_layout_init 0x0010 0xffff -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 - -source [find board/quark_se.cfg] diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index b925de4f896..9a572824164 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -26,9 +26,7 @@ if("${ARCH}" STREQUAL "arm") message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined") endif() elseif("${ARCH}" STREQUAL "arc") - if(CONFIG_SOC_QUARK_SE_C1000_SS) - set(GCC_M_CPU quarkse_em) - elseif(CONFIG_CPU_EM4_FPUS) + if(CONFIG_CPU_EM4_FPUS) set(GCC_M_CPU em4_fpus) elseif(CONFIG_CPU_EM4_DMIPS) set(GCC_M_CPU em4_dmips) diff --git a/doc/guides/test/sanitycheck.rst b/doc/guides/test/sanitycheck.rst index 2d7ac539fd5..2b7c1330ebc 100644 --- a/doc/guides/test/sanitycheck.rst +++ b/doc/guides/test/sanitycheck.rst @@ -519,9 +519,9 @@ filter: The ':' operator compiles the string argument as a regular expression, and then returns a true value only if the symbol's value in the environment - matches. For example, if CONFIG_SOC="quark_se" then + matches. For example, if CONFIG_SOC="stm32f107xc" then - filter = CONFIG_SOC : "quark.*" + filter = CONFIG_SOC : "stm.*" Would match it. diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index 663d312901b..71e47b4c7f9 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -37,7 +37,6 @@ add_subdirectory_if_kconfig(espi) add_subdirectory_ifdef(CONFIG_FLASH_HAS_DRIVER_ENABLED flash) add_subdirectory_ifdef(CONFIG_SERIAL_HAS_DRIVER serial) -add_subdirectory_ifdef(CONFIG_AIO_COMPARATOR aio) add_subdirectory_ifdef(CONFIG_BT bluetooth) add_subdirectory_ifdef(CONFIG_NETWORKING net) add_subdirectory_ifdef(CONFIG_NET_L2_ETHERNET ethernet) diff --git a/drivers/Kconfig b/drivers/Kconfig index 7ead7b53218..51a7169744d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -57,8 +57,6 @@ source "drivers/ptp_clock/Kconfig" source "drivers/ipm/Kconfig" -source "drivers/aio/Kconfig" - source "drivers/flash/Kconfig" source "drivers/sensor/Kconfig" diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index ad3babfb177..31b4353c636 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -8,7 +8,6 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c) zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c) zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c) zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC adc_nrfx_saadc.c) -zephyr_library_sources_ifdef(CONFIG_ADC_INTEL_QUARK_SE_C1000_SS adc_intel_quark_se_c1000_ss.c) zephyr_library_sources_ifdef(CONFIG_ADC_SAM0 adc_sam0.c) zephyr_library_sources_ifdef(CONFIG_ADC_STM32 adc_stm32.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE adc_handlers.c) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 4121a6d3386..55bda5bc98b 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -61,8 +61,6 @@ source "drivers/adc/Kconfig.nrfx" source "drivers/adc/Kconfig.sam_afec" -source "drivers/adc/Kconfig.intel_quark" - source "drivers/adc/Kconfig.sam0" source "drivers/adc/Kconfig.stm32" diff --git a/drivers/adc/Kconfig.intel_quark b/drivers/adc/Kconfig.intel_quark deleted file mode 100644 index 50d94b415ec..00000000000 --- a/drivers/adc/Kconfig.intel_quark +++ /dev/null @@ -1,71 +0,0 @@ -# Kconfig - ADC configuration options - -# -# Copyright (c) 2018-2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -menuconfig ADC_INTEL_QUARK_SE_C1000_SS - bool "ADC Driver for Intel Quark SE C1000 Sensor Subsystem" - depends on SOC_QUARK_SE_C1000_SS - select ADC_0 - help - Enable the ADC driver implementation of the Intel Quark SE C1000 - Sensor Subsystem. - -if ADC_INTEL_QUARK_SE_C1000_SS - -config ADC_INTEL_QUARK_SE_C1000_SS_CALIBRATION - bool "Enable Calibration" - default y - help - Enables ADC to run with a calibrated output at the - expense of execution speed when exiting low power states. - If disabled, the ADC will require the application/system-integrator - to provide a calibration method. - -choice - prompt "Output Mode" - default ADC_INTEL_QUARK_SE_C1000_SS_SERIAL - help - ADC output mode: parallel or serial. - -config ADC_INTEL_QUARK_SE_C1000_SS_SERIAL - bool "Serial" - -config ADC_INTEL_QUARK_SE_C1000_SS_PARALLEL - bool "Parallel" - -endchoice - -choice - prompt "Capture Mode" - default ADC_INTEL_QUARK_SE_C1000_SS_RISING_EDGE - help - ADC controller capture mode: - by rising or falling edge of adc_clk - -config ADC_INTEL_QUARK_SE_C1000_SS_RISING_EDGE - bool "Rising Edge" - -config ADC_INTEL_QUARK_SE_C1000_SS_FALLING_EDGE - bool "Falling Edge" - -endchoice - -config ADC_INTEL_QUARK_SE_C1000_SS_SERIAL_DELAY - int "Serial Delay" - default 1 - help - Number of ADC clock ticks that the first bit of - the serial output is delayed after the conversion - has started. - -config ADC_INTEL_QUARK_SE_C1000_SS_CLOCK_RATIO - int "Clock Ratio" - default 1024 - help - ADC Clock Ratio - -endif # ADC_INTEL_QUARK_SE_C1000_SS diff --git a/drivers/adc/adc_intel_quark_se_c1000_ss.c b/drivers/adc/adc_intel_quark_se_c1000_ss.c deleted file mode 100644 index 72a3f2928e2..00000000000 --- a/drivers/adc/adc_intel_quark_se_c1000_ss.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Copyright (c) 2015-2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Intel Quark SE C1000 Sensor Subsystem ADC Driver - * - * This is the driver for the ADC block in the Intel Quark SE C1000 - * Sensor Subsystem. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADC_CONTEXT_USES_KERNEL_TIMER -#include "adc_context.h" -#include "adc_intel_quark_se_c1000_ss.h" - -#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL -#include -LOG_MODULE_REGISTER(adc_intel_quark_se_c1000_ss); - -/* MST */ -#define ADC_CLOCK_GATE BIT(31) -#define ADC_CAL_REQ BIT(16) -#define ADC_DEEP_POWER_DOWN 0x01 -#define ADC_POWER_DOWN 0x01 -#define ADC_STANDBY 0x02 -#define ADC_NORMAL_WITH_CALIB 0x03 -#define ADC_NORMAL_WO_CALIB 0x04 -#define ADC_MODE_MASK 0x07 -#define ADC_DELAY_MASK (0xFFF8) -#define ADC_DELAY_POS 3 -#define ADC_DELAY_32MHZ (160 << ADC_DELAY_POS) - -/* SLV0 */ -#define ADC_CAL_ACK BIT(4) -#define ADC_PWR_MODE_STS BIT(3) - -#define ONE_BIT_SET 0x1 -#define THREE_BITS_SET 0x7 -#define FIVE_BITS_SET 0x1f -#define SIX_BITS_SET 0x3f -#define SEVEN_BITS_SET 0xef -#define ELEVEN_BITS_SET 0x7ff - -#define CAPTURE_MODE_POS 6 -#define OUTPUT_MODE_POS 7 -#define SERIAL_DELAY_POS 8 -#define SEQUENCE_MODE_POS 13 -#define SEQ_ENTRIES_POS 16 -#define THRESHOLD_POS 24 - -#define SEQ_MUX_EVEN_POS 0 -#define SEQ_DELAY_EVEN_POS 5 -#define SEQ_MUX_ODD_POS 16 -#define SEQ_DELAY_ODD_POS 21 - -#define ADC_NONE_CALIBRATION (0x80) - -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS -#define int_unmask(__mask) \ - sys_write32(sys_read32((__mask)) & ENABLE_SSS_INTERRUPTS, (__mask)) -#else -#define int_unmask(...) { ; } -#endif -static void adc_config_irq(void); - - -struct adc_info adc_info_dev = { - ADC_CONTEXT_INIT_TIMER(adc_info_dev, ctx), - ADC_CONTEXT_INIT_LOCK(adc_info_dev, ctx), - ADC_CONTEXT_INIT_SYNC(adc_info_dev, ctx), - .state = ADC_STATE_IDLE, -#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CALIBRATION - .calibration_value = ADC_NONE_CALIBRATION, -#endif -}; - -static inline void wait_slv0_bit_set(u32_t bit_mask) -{ - u32_t reg_value; - - do { - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0); - } while ((reg_value & bit_mask) == 0U); -} - -static void set_power_mode_inner(u32_t mode) -{ - u32_t reg_value; - u32_t state; - - state = irq_lock(); - - /* Request Power Down first before transitioning */ - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0); - - reg_value &= ~(ADC_MODE_MASK); - reg_value |= mode; - - sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0); - - irq_unlock(state); - - /* Wait for power mode to be set */ - wait_slv0_bit_set(ADC_PWR_MODE_STS); -} - -static void set_power_mode(u32_t mode) -{ - u32_t reg_value; - - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0); - - /* no need to set if power mode is the same as requested */ - if ((reg_value & ADC_MODE_MASK) == mode) { - return; - } - - /* Request Power Down first before transitioning */ - set_power_mode_inner(ADC_POWER_DOWN); - - /* Then set to the desired mode */ - set_power_mode_inner(mode); -} - -/* - * A dummy conversion is needed after coming out of deep - * power down, or else the first conversion would not be - * correct. - */ -static void dummy_conversion(struct device *dev) -{ - const struct adc_config *config = dev->config->config_info; - u32_t adc_base = config->reg_base; - u32_t reg_value; - - /* Flush FIFO */ - reg_value = sys_in32(adc_base + ADC_SET); - reg_value |= ADC_SET_FLUSH_RX; - sys_out32(reg_value, adc_base + ADC_SET); - - /* Reset sequence table */ - reg_value = sys_in32(adc_base + ADC_CTRL); - reg_value |= ADC_CTRL_SEQ_TABLE_RST; - sys_out32(reg_value, adc_base + ADC_CTRL); - - /* Setup sequence table for dummy */ - sys_out32((10 << 5), adc_base + ADC_SEQ); - - /* - * Set number of entries in sequencer (n-1) - * and threshold to generate interrupt. - */ - reg_value = sys_in32(adc_base + ADC_SET); - reg_value &= ~(ADC_SET_SEQ_ENTRIES_MASK | ADC_SET_THRESHOLD_MASK); - sys_out32(reg_value, adc_base + ADC_SET); - - /* - * Reset sequence pointer, - * Clear and mask interrupts, - * Enable ADC and start sequencer. - */ - reg_value = sys_in32(adc_base + ADC_CTRL); - reg_value |= ADC_CTRL_SEQ_PTR_RST | ADC_CTRL_INT_CLR_ALL | - ADC_CTRL_INT_MASK_ALL | ADC_CTRL_ENABLE | - ADC_CTRL_SEQ_START; - sys_out32(reg_value, adc_base + ADC_CTRL); - - /* Wait for data available */ - do { - reg_value = sys_in32(adc_base + ADC_INTSTAT); - } while ((reg_value & ADC_INTSTAT_DATA_A) == 0U); - - /* Flush FIFO */ - reg_value = sys_in32(adc_base + ADC_SET); - reg_value |= ADC_SET_FLUSH_RX; - sys_out32(reg_value, adc_base + ADC_SET); - - /* Clear data available interrupt and disable ADC */ - reg_value = sys_in32(adc_base + ADC_CTRL); - reg_value |= ADC_CTRL_CLR_DATA_A; - reg_value &= ~ADC_CTRL_ENABLE; - sys_out32(reg_value, adc_base + ADC_CTRL); -} - -#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CALIBRATION -static void calibration_command(u8_t command) -{ - u32_t state; - u32_t reg_value; - - /* Set Calibration Request */ - state = irq_lock(); - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0); - reg_value |= (command & THREE_BITS_SET) << 17; - reg_value |= ADC_CAL_REQ; - sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0); - irq_unlock(state); - - /* Waiting for calibration ack */ - wait_slv0_bit_set(ADC_CAL_ACK); - - /* Clear Calibration Request once done */ - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0); - reg_value &= ~ADC_CAL_REQ; - sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0); -} - -static void adc_goto_normal_mode(struct device *dev) -{ - struct adc_info *info = dev->driver_data; - u8_t calibration_value; - u32_t reg_value; - - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0); - - if ((reg_value & ADC_MODE_MASK) != ADC_NORMAL_WITH_CALIB) { - - /* Request Normal With Calibration Mode */ - set_power_mode(ADC_NORMAL_WITH_CALIB); - - /* Poll waiting for normal mode with calibration */ - wait_slv0_bit_set(ADC_PWR_MODE_STS); - - if (info->calibration_value == ADC_NONE_CALIBRATION) { - /* Reset Calibration */ - calibration_command(ADC_CMD_RESET_CALIBRATION); - /* Request Calibration */ - calibration_command(ADC_CMD_START_CALIBRATION); - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0); - calibration_value = (reg_value >> 5) & SEVEN_BITS_SET; - info->calibration_value = calibration_value; - } - - /* Load Calibration */ - reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0); - reg_value |= (info->calibration_value << 20); - sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0); - calibration_command(ADC_CMD_LOAD_CALIBRATION); - } - - dummy_conversion(dev); -} - -#else -static void adc_goto_normal_mode(struct device *dev) -{ - ARG_UNUSED(dev); - - /* Request Normal Without Calibration Mode */ - set_power_mode(ADC_NORMAL_WO_CALIB); - - dummy_conversion(dev); -} -#endif - -static int set_resolution(struct device *dev, - const struct adc_sequence *sequence) -{ - u32_t tmp_val; - const struct adc_config *config = dev->config->config_info; - u32_t adc_base = config->reg_base; - - tmp_val = sys_in32(adc_base + ADC_SET); - tmp_val &= ~FIVE_BITS_SET; - - switch (sequence->resolution) { - case 6: - break; - case 8: - tmp_val |= 1 & FIVE_BITS_SET; - break; - case 10: - tmp_val |= 2 & FIVE_BITS_SET; - break; - case 12: - tmp_val |= 3 & FIVE_BITS_SET; - break; - default: - return -EINVAL; - } - - sys_out32(tmp_val, adc_base + ADC_SET); - - return 0; -} - -/* Implementation of the ADC driver API function: adc_channel_setup. */ -static int adc_quark_se_ss_channel_setup( - struct device *dev, - const struct adc_channel_cfg *channel_cfg - ) -{ - u8_t channel_id = channel_cfg->channel_id; - struct adc_info *info = dev->driver_data; - - if (channel_id >= DW_CHANNEL_COUNT) { - LOG_ERR("Invalid channel id"); - return -EINVAL; - } - - if (channel_cfg->gain != ADC_GAIN_1) { - LOG_ERR("Invalid channel gain"); - return -EINVAL; - } - - if (channel_cfg->reference != ADC_REF_INTERNAL) { - LOG_ERR("Invalid channel reference"); - return -EINVAL; - } - - if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { - LOG_ERR("Invalid channel acquisition time"); - return -EINVAL; - } - - if (info->state != ADC_STATE_IDLE) { - LOG_ERR("ADC is busy or in error state"); - return -EAGAIN; - } - - info->active_channels |= 1 << channel_id; - return 0; -} - -static int adc_quark_se_ss_read_request(struct device *dev, - const struct adc_sequence *seq_tbl) -{ - struct adc_info *info = dev->driver_data; - int error = 0; - u32_t utmp, num_channels, interval = 0U; - - info->channels = seq_tbl->channels & info->active_channels; - - if (seq_tbl->channels != info->channels) { - return -EINVAL; - } - - error = set_resolution(dev, seq_tbl); - if (error) { - return error; - } - - /* - * Make sure the requested interval is longer than the time - * needed to do one conversion. - */ - if (seq_tbl->options && - (seq_tbl->options->interval_us > 0)) { - /* - * System clock is 32MHz, which means 1us == 32 cycles - * if divider is 1. - */ - interval = seq_tbl->options->interval_us * 32U / - CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CLOCK_RATIO; - - if (interval < (seq_tbl->resolution + 2)) { - return -EINVAL; - } - } - - info->entries = seq_tbl; - info->buffer = (u16_t *)seq_tbl->buffer; - - /* check if buffer has enough size */ - utmp = info->channels; - num_channels = 0U; - while (utmp) { - if (utmp & BIT(0)) { - num_channels++; - } - utmp >>= 1; - } - utmp = num_channels * sizeof(u16_t); - - if (seq_tbl->options) { - utmp *= (1 + seq_tbl->options->extra_samplings); - } - - if (utmp > seq_tbl->buffer_size) { - return -ENOMEM; - } - - info->state = ADC_STATE_SAMPLING; - - adc_context_start_read(&info->ctx, seq_tbl); - error = adc_context_wait_for_completion(&info->ctx); - - if (info->state == ADC_STATE_ERROR) { - info->state = ADC_STATE_IDLE; - return -EIO; - } - - return error; -} - -static int adc_quark_se_ss_read(struct device *dev, - const struct adc_sequence *seq_tbl) -{ - struct adc_info *info = dev->driver_data; - int ret; - - adc_context_lock(&info->ctx, false, NULL); - ret = adc_quark_se_ss_read_request(dev, seq_tbl); - adc_context_release(&info->ctx, ret); - - return ret; -} - -#ifdef CONFIG_ADC_ASYNC -/* Implementation of the ADC driver API function: adc_read_async. */ -static int adc_quark_se_ss_read_async(struct device *dev, - const struct adc_sequence *sequence, - struct k_poll_signal *async) -{ - struct adc_info *info = dev->driver_data; - int ret; - - adc_context_lock(&info->ctx, true, async); - ret = adc_quark_se_ss_read_request(dev, sequence); - adc_context_release(&info->ctx, ret); - - return ret; -} -#endif - -static void adc_quark_se_ss_start_conversion(struct device *dev) -{ - struct adc_info *info = dev->driver_data; - const struct adc_config *config = info->dev->config->config_info; - const struct adc_sequence *entry = &info->ctx.sequence; - u32_t adc_base = config->reg_base; - u32_t ctrl, tmp_val, sample_window; - - info->channel_id = find_lsb_set(info->channels) - 1; - - /* Flush FIFO */ - tmp_val = sys_in32(adc_base + ADC_SET); - tmp_val |= ADC_SET_FLUSH_RX; - sys_out32(tmp_val, adc_base + ADC_SET); - - /* Reset sequence table */ - ctrl = sys_in32(adc_base + ADC_CTRL); - ctrl |= ADC_CTRL_SEQ_TABLE_RST; - sys_out32(ctrl, adc_base + ADC_CTRL); - - /* - * Hardware requires min (resolution + 2) cycles, - * or will emit SEQERROR. - */ - sample_window = entry->resolution + 2; - tmp_val = (sample_window & ELEVEN_BITS_SET) << SEQ_DELAY_EVEN_POS; - tmp_val |= (info->channel_id & FIVE_BITS_SET); - - sys_out32(tmp_val, adc_base + ADC_SEQ); - - /* - * Clear number of entries in sequencer and threshold to generate - * interrupt, since only 1 conversion is needed and fields are - * zero-based. - */ - tmp_val = sys_in32(adc_base + ADC_SET); - tmp_val &= ~(ADC_SET_SEQ_ENTRIES_MASK | ADC_SET_THRESHOLD_MASK); - sys_out32(tmp_val, adc_base + ADC_SET); - - /* - * Reset sequence pointer, - * Clear and unmask interrupts, - * Enable ADC and start sequencer. - */ - ctrl = sys_in32(adc_base + ADC_CTRL); - ctrl &= ~ADC_CTRL_INT_MASK_ALL; - ctrl |= ADC_CTRL_SEQ_PTR_RST | ADC_CTRL_INT_CLR_ALL | - ADC_CTRL_ENABLE | ADC_CTRL_SEQ_START; - sys_out32(ctrl, adc_base + ADC_CTRL); -} - -static void adc_context_start_sampling(struct adc_context *ctx) -{ - struct adc_info *info = CONTAINER_OF(ctx, struct adc_info, ctx); - - info->channels = ctx->sequence.channels; - - adc_quark_se_ss_start_conversion(info->dev); -} - -static void adc_context_update_buffer_pointer(struct adc_context *ctx, - bool repeat) -{ - struct adc_info *info = CONTAINER_OF(ctx, struct adc_info, ctx); - const struct adc_sequence *entry = &ctx->sequence; - - if (repeat) { - info->buffer = (u16_t *)entry->buffer; - } -} - -int adc_quark_se_ss_init(struct device *dev) -{ - u32_t val; - const struct adc_config *config = dev->config->config_info; - u32_t adc_base = config->reg_base; - struct adc_info *info = dev->driver_data; - - /* Disable clock gating */ - val = sys_in32(PERIPH_ADDR_BASE_CREG_MST0); - val &= ~(ADC_CLOCK_GATE); - sys_out32(val, PERIPH_ADDR_BASE_CREG_MST0); - - /* Mask all interrupts and enable clock */ - val = ADC_CTRL_INT_MASK_ALL | ADC_CTRL_CLK_ENABLE; - sys_out32(val, adc_base + ADC_CTRL); - - /* Configure common properties */ - val = ((config->capture_mode & ONE_BIT_SET) << CAPTURE_MODE_POS); - val |= ((config->out_mode & ONE_BIT_SET) << OUTPUT_MODE_POS); - val |= ((config->serial_dly & FIVE_BITS_SET) << SERIAL_DELAY_POS); - val |= ((config->seq_mode & ONE_BIT_SET) << SEQUENCE_MODE_POS); - val &= ~(ADC_SET_INPUT_MODE_MASK); - sys_out32(val, adc_base + ADC_SET); - - /* Set the clock ratio */ - sys_out32(config->clock_ratio & ADC_DIVSEQSTAT_CLK_RATIO_MASK, - adc_base + ADC_DIVSEQSTAT); - - config->config_func(); - - int_unmask(config->reg_irq_mask); - int_unmask(config->reg_err_mask); - - info->dev = dev; - - adc_goto_normal_mode(dev); - - info->state = ADC_STATE_IDLE; - - adc_context_unlock_unconditionally(&info->ctx); - return 0; -} - -static void adc_quark_se_ss_rx_isr(void *arg) -{ - struct device *dev = (struct device *)arg; - struct adc_info *info = dev->driver_data; - const struct adc_config *config = dev->config->config_info; - struct adc_sequence *seq = &info->ctx.sequence; - u32_t adc_base = config->reg_base; - u32_t reg_val; - - /* Pop data from FIFO and put it into buffer */ - reg_val = sys_in32(adc_base + ADC_SET); - reg_val |= ADC_SET_POP_RX; - sys_out32(reg_val, adc_base + ADC_SET); - - /* Sample is always 12-bit, so need to shift */ - *info->buffer++ = sys_in32(adc_base + ADC_SAMPLE) >> - (12 - seq->resolution); - - /* Clear data available register */ - reg_val = sys_in32(adc_base + ADC_CTRL); - reg_val |= ADC_CTRL_CLR_DATA_A; - sys_out32(reg_val, adc_base + ADC_CTRL); - - /* Stop sequencer and mask all interrupts */ - reg_val = sys_in32(adc_base + ADC_CTRL); - reg_val &= ~ADC_CTRL_SEQ_START; - reg_val |= ADC_CTRL_INT_MASK_ALL; - sys_out32(reg_val, adc_base + ADC_CTRL); - - /* Disable ADC */ - reg_val = sys_in32(adc_base + ADC_CTRL); - reg_val &= ~ADC_CTRL_ENABLE; - sys_out32(reg_val, adc_base + ADC_CTRL); - - info->state = ADC_STATE_IDLE; - info->channels &= ~BIT(info->channel_id); - - if (info->channels) { - adc_quark_se_ss_start_conversion(dev); - } else { - adc_context_on_sampling_done(&info->ctx, dev); - } -} - -static void adc_quark_se_ss_err_isr(void *arg) -{ - struct device *dev = (struct device *) arg; - const struct adc_config *config = dev->config->config_info; - struct adc_info *info = dev->driver_data; - u32_t adc_base = config->reg_base; - u32_t reg_val = sys_in32(adc_base + ADC_SET); - - /* - * Stop sequencer, mask/clear all interrupts, - * and disable ADC. - */ - reg_val = sys_in32(adc_base + ADC_CTRL); - reg_val &= ~(ADC_CTRL_SEQ_START | ADC_CTRL_ENABLE); - reg_val |= ADC_CTRL_INT_MASK_ALL; - reg_val |= ADC_CTRL_INT_CLR_ALL; - sys_out32(reg_val, adc_base + ADC_CTRL); - - info->state = ADC_STATE_ERROR; - adc_context_on_sampling_done(&info->ctx, dev); -} - -static const struct adc_driver_api api_funcs = { - .channel_setup = adc_quark_se_ss_channel_setup, - .read = adc_quark_se_ss_read, -#ifdef CONFIG_ADC_ASYNC - .read_async = adc_quark_se_ss_read_async, -#endif -}; - -const static struct adc_config adc_config_dev = { - .reg_base = DT_ADC_0_BASE_ADDRESS, - .reg_irq_mask = SCSS_REGISTER_BASE + INT_SS_ADC_IRQ_MASK, - .reg_err_mask = SCSS_REGISTER_BASE + INT_SS_ADC_ERR_MASK, -#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_SERIAL - .out_mode = 0, -#elif CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_PARALLEL - .out_mode = 1, -#endif - .seq_mode = 0, - -#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_RISING_EDGE - .capture_mode = 0, -#elif CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_FALLING_EDGE - .capture_mode = 1, -#endif - .clock_ratio = CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CLOCK_RATIO, - .serial_dly = CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_SERIAL_DELAY, - .config_func = adc_config_irq, -}; - -DEVICE_AND_API_INIT(adc_quark_se_ss, DT_ADC_0_NAME, &adc_quark_se_ss_init, - &adc_info_dev, &adc_config_dev, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &api_funcs); - -static void adc_config_irq(void) -{ - IRQ_CONNECT(DT_ADC_0_IRQ, DT_ADC_0_IRQ_PRI, adc_quark_se_ss_rx_isr, - DEVICE_GET(adc_quark_se_ss), 0); - irq_enable(DT_ADC_0_IRQ); - - IRQ_CONNECT(DT_ADC_IRQ_ERR, DT_ADC_0_IRQ_PRI, - adc_quark_se_ss_err_isr, DEVICE_GET(adc_quark_se_ss), 0); - irq_enable(DT_ADC_IRQ_ERR); -} diff --git a/drivers/adc/adc_intel_quark_se_c1000_ss.h b/drivers/adc/adc_intel_quark_se_c1000_ss.h deleted file mode 100644 index 0bac80139d9..00000000000 --- a/drivers/adc/adc_intel_quark_se_c1000_ss.h +++ /dev/null @@ -1,202 +0,0 @@ -/** - * Copyright (c) 2015-2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -/** - * @file - * - * @brief Designware ADC header file - */ - -#ifndef ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_ -#define ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * ADC driver name. - * - * Name for the singleton instance of the ADC driver. - * - */ -#define ADC_DRV_NAME "adc" - -/** - * Number of buffers. - * - * Number of reception buffers to be supported by the driver. - */ -#define BUFS_NUM 32 - -/* EAI ADC device registers */ -#define ADC_SET (0x00) -#define ADC_DIVSEQSTAT (0x01) -#define ADC_SEQ (0x02) -#define ADC_CTRL (0x03) -#define ADC_INTSTAT (0x04) -#define ADC_SAMPLE (0x05) - -/* Sensor Subsystem Interrupt Routing Mask */ -#define INT_SS_ADC_ERR_MASK (0x400) -#define INT_SS_ADC_IRQ_MASK (0x404) - -/* ADC_DIVSEQSTAT register */ -#define ADC_DIVSEQSTAT_CLK_RATIO_MASK (0x1fffff) - -/* ADC_SET register */ -#define ADC_SET_POP_RX BIT(31) -#define ADC_SET_FLUSH_RX BIT(30) -#define ADC_SET_SEQ_MODE_MASK BIT(13) -#define ADC_SET_INPUT_MODE_MASK BIT(5) -#define ADC_SET_THRESHOLD_MASK (0x3F000000) -#define ADC_SET_THRESHOLD_POS 24 -#define ADC_SET_SEQ_ENTRIES_MASK (0x003F0000) -#define ADC_SET_SEQ_ENTRIES_POS 16 - -/* ADC_CTRL register */ -#define ADC_CTRL_CLR_DATA_A BIT(16) -#define ADC_CTRL_SEQ_TABLE_RST BIT(6) -#define ADC_CTRL_SEQ_PTR_RST BIT(5) -#define ADC_CTRL_SEQ_START BIT(4) -#define ADC_CTRL_CLK_ENABLE BIT(2) -#define ADC_CTRL_INT_CLR_ALL (0x000F0000) -#define ADC_CTRL_INT_MASK_ALL (0x00000F00) - -#define ADC_CTRL_ENABLE BIT(1) -#define ADC_CTRL_DISABLE (0x0) - -/* ADC_INTSTAT register */ -#define ADC_INTSTAT_SEQERROR BIT(3) -#define ADC_INTSTAT_UNDERFLOW BIT(2) -#define ADC_INTSTAT_OVERFLOW BIT(1) -#define ADC_INTSTAT_DATA_A BIT(0) - -#define ADC_STATE_CLOSED 0 -#define ADC_STATE_DISABLED 1 -#define ADC_STATE_IDLE 2 -#define ADC_STATE_SAMPLING 3 -#define ADC_STATE_ERROR 4 - -#define ADC_CMD_RESET_CALIBRATION 2 -#define ADC_CMD_START_CALIBRATION 3 -#define ADC_CMD_LOAD_CALIBRATION 4 - -#define IO_ADC_SET_CLK_DIVIDER (0x20) -#define IO_ADC_SET_CONFIG (0x21) -#define IO_ADC_SET_SEQ_TABLE (0x22) -#define IO_ADC_SET_SEQ_MODE (0x23) -#define IO_ADC_SET_SEQ_STOP (0x24) -#define IO_ADC_SET_RX_THRESHOLD (0x25) - -#define IO_ADC_INPUT_SINGLE_END 0 -#define IO_ADC_INPUT_DIFF 1 -#define IO_ADC_OUTPUT_PARAL 0 -#define IO_ADC_OUTPUT_SERIAL 1 -#define IO_ADC_CAPTURE_RISING_EDGE 0 -#define IO_ADC_CAPTURE_FALLING_EDGE 1 - -#define IO_ADC_SEQ_MODE_SINGLESHOT 0 -#define IO_ADC_SEQ_MODE_REPETITIVE 1 - -#define ENABLE_SSS_INTERRUPTS ~(0x01 << 8) - -#define ENABLE_ADC \ - ( \ - ADC_CTRL_CLK_ENABLE \ - | ADC_CTRL_SEQ_TABLE_RST \ - | ADC_CTRL_SEQ_PTR_RST \ - ) - -#define START_ADC_SEQ \ - ( \ - ADC_CTRL_SEQ_START \ - | ADC_CTRL_ENABLE \ - | ADC_CTRL_CLK_ENABLE \ - ) - -#define DW_CHANNEL_COUNT 19 - -/** mV = 3.3V*/ -#define ADC_VREF 3300 - -/** - * - * @brief Converts ADC raw data into mV - * - * The ADC raw data readings are converted into mV: - * result = (data * ADC_VREF) / (2^resolution). - * - * @param _data_ Raw data to be converted. - * @param _resolution_ Resolution used during the data sampling. - * - * @return data read in mVolts. - */ -#define ss_adc_data_to_mv(_data_, _resolution_) \ - ((_data_ * ADC_VREF) / (1 << _resolution_)) - -typedef void (*adc_intel_quark_se_c1000_ss_config_t)(void); -/** @brief ADC configuration - * This structure defines the ADC configuration values - * that define the ADC hardware instance and configuration. - */ -struct adc_config { - /**Register base address for hardware registers.*/ - u32_t reg_base; - /**IIO address for the IRQ mask register.*/ - u32_t reg_irq_mask; - /**IIO address for the error mask register.*/ - u32_t reg_err_mask; - /**Output mode*/ - u8_t out_mode; - /**Capture mode*/ - u8_t capture_mode; - /**Sequence mode*/ - u8_t seq_mode; - /**Serial delay*/ - u8_t serial_dly; - /**Sample width*/ - u8_t sample_width; - u8_t padding[3]; - /**Clock ratio*/ - u32_t clock_ratio; - /**Config handler*/ - adc_intel_quark_se_c1000_ss_config_t config_func; -}; - -/**@brief ADC information and data. - * - * This structure defines the data that will be used - * during driver execution. - */ -struct adc_info { - struct device *dev; - struct adc_context ctx; - u16_t *buffer; - u32_t active_channels; - u32_t channels; - u32_t channel_id; - - /**Sequence entries' array*/ - const struct adc_sequence *entries; - /**State of execution of the driver*/ - u8_t state; - /**Sequence size*/ - u8_t seq_size; -#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CALIBRATION - /**Calibration value*/ - u8_t calibration_value; -#endif - -}; - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_ */ diff --git a/drivers/aio/CMakeLists.txt b/drivers/aio/CMakeLists.txt deleted file mode 100644 index 22621d6bfdd..00000000000 --- a/drivers/aio/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources_ifdef(CONFIG_AIO_COMPARATOR_QMSI aio_comparator_qmsi.c) -zephyr_library_sources_ifdef(CONFIG_USERSPACE aio_comparator_handlers.c) diff --git a/drivers/aio/Kconfig b/drivers/aio/Kconfig deleted file mode 100644 index c02012c77ee..00000000000 --- a/drivers/aio/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Kconfig - AIO/Comparator configuration options -# -# -# Copyright (c) 2015-2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -# -# AIO/Comparator options -# -menuconfig AIO_COMPARATOR - bool "AIO/Comparator Configuration" - -if AIO_COMPARATOR -menuconfig AIO_COMPARATOR_QMSI - bool "Enable QMSI AIO/comparator driver" - depends on QMSI - help - QMSI AIO/Comparator driver. - -config AIO_COMPARATOR_0_NAME - string "Device name for AIO/comparator" - default "AIO_CMP_0" - help - Device name for the AIO/comparator. - -config AIO_COMPARATOR_0_IRQ_PRI - int "IRQ Priority for AIO/comparator" - default 3 - help - IRQ Priority for the AIO/comparator. - -endif # AIO_COMPARATOR diff --git a/drivers/aio/aio_comparator_handlers.c b/drivers/aio/aio_comparator_handlers.c deleted file mode 100644 index 8c6fa157707..00000000000 --- a/drivers/aio/aio_comparator_handlers.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -Z_SYSCALL_HANDLER(aio_cmp_disable, dev, index) -{ - Z_OOPS(Z_SYSCALL_DRIVER_AIO_CMP(dev, disable)); - return z_impl_aio_cmp_disable((struct device *)dev, index); -} - -Z_SYSCALL_HANDLER(aio_cmp_get_pending_int, dev) -{ - Z_OOPS(Z_SYSCALL_DRIVER_AIO_CMP(dev, get_pending_int)); - return z_impl_aio_get_pending_int((struct device *)dev, index); -} diff --git a/drivers/aio/aio_comparator_qmsi.c b/drivers/aio/aio_comparator_qmsi.c deleted file mode 100644 index 87a990f5c40..00000000000 --- a/drivers/aio/aio_comparator_qmsi.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include "qm_comparator.h" - -#define INT_COMPARATORS_MASK 0x7FFFF -#define AIO_QMSI_CMP_COUNT (19) -#if (QM_LAKEMONT) -#define CMP_INTR_ROUTER QM_INTERRUPT_ROUTER->comparator_0_host_int_mask -#else -#define CMP_INTR_ROUTER QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask -#endif - -struct aio_qmsi_cmp_cb { - aio_cmp_cb cb; - void *param; -}; - -struct aio_qmsi_cmp_dev_data_t { - /** Number of total comparators */ - u8_t num_cmp; - /** Callback for each comparator */ - struct aio_qmsi_cmp_cb cb[AIO_QMSI_CMP_COUNT]; -}; - -/* Shadow configuration to keep track of changes */ -static qm_ac_config_t config; - -static int aio_cmp_config(struct device *dev); - -static int aio_qmsi_cmp_disable(struct device *dev, u8_t index) -{ - if (index >= AIO_QMSI_CMP_COUNT) { - return -EINVAL; - } - - /* Disable interrupt to current core */ - CMP_INTR_ROUTER |= (1 << index); - - /* Disable comparator according to index */ - config.cmp_en &= ~(1 << index); - config.power &= ~(1 << index); - config.reference &= ~(1 << index); - config.polarity &= ~(1 << index); - - if (qm_ac_set_config(&config) != 0) { - return -EINVAL; - } - - return 0; -} - -static int aio_qmsi_cmp_configure(struct device *dev, u8_t index, - enum aio_cmp_polarity polarity, - enum aio_cmp_ref refsel, - aio_cmp_cb cb, void *param) -{ - struct aio_qmsi_cmp_dev_data_t *dev_data = - (struct aio_qmsi_cmp_dev_data_t *)dev->driver_data; - - if (index >= AIO_QMSI_CMP_COUNT) { - return -EINVAL; - } - - aio_qmsi_cmp_disable(dev, index); - - dev_data->cb[index].cb = cb; - dev_data->cb[index].param = param; - - if (refsel == AIO_CMP_REF_A) { - config.reference &= ~(1 << index); - } else { - config.reference |= (1 << index); - } - - if (polarity == AIO_CMP_POL_RISE) { - config.polarity &= ~(1 << index); - } else { - config.polarity |= (1 << index); - } - /* The driver will not use QMSI callback mechanism */ - config.callback = NULL; - /* Enable comparator */ - config.cmp_en |= (1 << index); - config.power |= (1 << index); - - if (qm_ac_set_config(&config) != 0) { - return -EINVAL; - } - - /* Enable Interrupts to current core for an specific comparator */ - CMP_INTR_ROUTER &= ~(1 << index); - - return 0; -} - -static u32_t aio_cmp_qmsi_get_pending_int(struct device *dev) -{ - return QM_SCSS_CMP->cmp_stat_clr; -} - -static const struct aio_cmp_driver_api aio_cmp_funcs = { - .disable = aio_qmsi_cmp_disable, - .configure = aio_qmsi_cmp_configure, - .get_pending_int = aio_cmp_qmsi_get_pending_int, -}; - -static int aio_qmsi_cmp_init(struct device *dev) -{ - u8_t i; - struct aio_qmsi_cmp_dev_data_t *dev_data = - (struct aio_qmsi_cmp_dev_data_t *)dev->driver_data; - - aio_cmp_config(dev); - - /* Disable all comparator interrupts */ - CMP_INTR_ROUTER |= INT_COMPARATORS_MASK; - - /* Clear status and dissble all comparators */ - QM_SCSS_CMP->cmp_stat_clr |= INT_COMPARATORS_MASK; - QM_SCSS_CMP->cmp_pwr &= ~INT_COMPARATORS_MASK; - QM_SCSS_CMP->cmp_en &= ~INT_COMPARATORS_MASK; - - /* Don't use the QMSI callback */ - config.callback = NULL; - /* Get Initial configuration from HW */ - config.reference = QM_SCSS_CMP->cmp_ref_sel; - config.polarity = QM_SCSS_CMP->cmp_ref_pol; - config.power = QM_SCSS_CMP->cmp_pwr; - config.cmp_en = QM_SCSS_CMP->cmp_en; - - /* Clear callback pointers */ - for (i = 0U; i < dev_data->num_cmp; i++) { - dev_data->cb[i].cb = NULL; - dev_data->cb[i].param = NULL; - } - - irq_enable(IRQ_GET_NUMBER(QM_IRQ_COMPARATOR_0_INT)); - - return 0; -} - -static void aio_qmsi_cmp_isr(void *data) -{ - u8_t i; - struct device *dev = data; - struct aio_qmsi_cmp_dev_data_t *dev_data = - (struct aio_qmsi_cmp_dev_data_t *)dev->driver_data; - - u32_t int_status = QM_SCSS_CMP->cmp_stat_clr; - - for (i = 0U; i < dev_data->num_cmp; i++) { - if (int_status & (1 << i)) { - if (dev_data->cb[i].cb != NULL) { - dev_data->cb[i].cb(dev_data->cb[i].param); - } - } - } - - /* Clear all pending interrupts */ - QM_SCSS_CMP->cmp_stat_clr = int_status; -} - -static struct aio_qmsi_cmp_dev_data_t aio_qmsi_cmp_dev_data = { - .num_cmp = AIO_QMSI_CMP_COUNT, -}; - -DEVICE_AND_API_INIT(aio_qmsi_cmp, CONFIG_AIO_COMPARATOR_0_NAME, - &aio_qmsi_cmp_init, &aio_qmsi_cmp_dev_data, NULL, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - (void *)&aio_cmp_funcs); - -static int aio_cmp_config(struct device *dev) -{ - ARG_UNUSED(dev); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_COMPARATOR_0_INT), - CONFIG_AIO_COMPARATOR_0_IRQ_PRI, aio_qmsi_cmp_isr, - DEVICE_GET(aio_qmsi_cmp), 0); - - return 0; -} diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 536fc52adeb..213b29a7b88 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -6,7 +6,6 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC clock_control_mcux zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_control_mcux_scg.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF nrf_power_clock.c) -zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE quark_se_clock_control.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c) if(CONFIG_CLOCK_CONTROL_STM32_CUBE) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index f63ea225570..cf97595dbbe 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -25,8 +25,6 @@ source "subsys/logging/Kconfig.template.log_config" source "drivers/clock_control/Kconfig.nrf" -source "drivers/clock_control/Kconfig.quark_se" - source "drivers/clock_control/Kconfig.stm32" source "drivers/clock_control/Kconfig.beetle" diff --git a/drivers/clock_control/Kconfig.quark_se b/drivers/clock_control/Kconfig.quark_se deleted file mode 100644 index b8d9e6b42c3..00000000000 --- a/drivers/clock_control/Kconfig.quark_se +++ /dev/null @@ -1,47 +0,0 @@ -# Kconfig - Clock controller driver configuration options - -# -# Copyright (c) 2015-2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -menuconfig CLOCK_CONTROL_QUARK_SE - bool "Quark SE Clock controller support" - help - Enable support for the Quark SE clock driver. - -if CLOCK_CONTROL_QUARK_SE - -config CLOCK_CONTROL_QUARK_SE_PERIPHERAL - bool "Quark SE peripheral clock support" - help - Enable support for Quark SE peripheral clock which controls the - clock of I2C, SPI, GPIO controllers and more. - -config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME - string "Quark SE peripheral clock device name" - depends on CLOCK_CONTROL_QUARK_SE_PERIPHERAL - default "clk_peripheral" - -config CLOCK_CONTROL_QUARK_SE_EXTERNAL - bool "Quark SE external clock support" - help - Enable support for Quark SE external sub-system clock. - -config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME - string "Quark SE external clock device name" - depends on CLOCK_CONTROL_QUARK_SE_EXTERNAL - default "clk_external" - -config CLOCK_CONTROL_QUARK_SE_SENSOR - bool "Quark SE sensor clock support" - help - Enable support for Quark SE sensor sub-system clock. - -config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME - string "Quark SE sensor clock device name" - depends on CLOCK_CONTROL_QUARK_SE_SENSOR - default "clk_sensor" - -endif # CLOCK_CONTROL_QUARK_SE diff --git a/drivers/clock_control/quark_se_clock_control.c b/drivers/clock_control/quark_se_clock_control.c deleted file mode 100644 index 871e8805dc7..00000000000 --- a/drivers/clock_control/quark_se_clock_control.c +++ /dev/null @@ -1,133 +0,0 @@ -/* quark_se_clock_control.c - Clock controller driver for Quark SE */ - -/* - * Copyright (c) 2015 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include - -#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL -#include -LOG_MODULE_REGISTER(clock_control); - -#ifdef CONFIG_ARC -#define WRITE(__data, __base_address) \ - sys_out32(__data, __base_address) -#define TEST_CLEAR_BIT(__base_address, __bit) \ - sys_io_test_and_clear_bit(__base_address, __bit) -#else -#define WRITE(__data, __base_address) \ - sys_write32(__data, __base_address) -#define TEST_CLEAR_BIT(__base_address, __bit) \ - sys_test_and_clear_bit(__base_address, __bit) -#endif /* CONFIG_ARC */ - -struct quark_se_clock_control_config { - u32_t base_address; -}; - -static inline int quark_se_clock_control_on(struct device *dev, - clock_control_subsys_t sub_system) -{ - const struct quark_se_clock_control_config *info = - dev->config->config_info; - u32_t subsys = POINTER_TO_INT(sub_system); - - if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) { - LOG_DBG("Enabling all clock gates on dev %p", dev); - WRITE(0xffffffff, info->base_address); - - return 0; - } - - LOG_DBG("Enabling clock gate on dev %p subsystem %u", dev, subsys); - - return TEST_CLEAR_BIT(info->base_address, subsys); -} - -static inline int quark_se_clock_control_off(struct device *dev, - clock_control_subsys_t sub_system) -{ - const struct quark_se_clock_control_config *info = - dev->config->config_info; - u32_t subsys = POINTER_TO_INT(sub_system); - - if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) { - LOG_DBG("Disabling all clock gates on dev %p", dev); - WRITE(0x00000000, info->base_address); - - return 0; - } - - LOG_DBG("clock gate on dev %p subsystem %u", dev, subsys); - - return TEST_CLEAR_BIT(info->base_address, subsys); -} - -static const struct clock_control_driver_api quark_se_clock_control_api = { - .on = quark_se_clock_control_on, - .off = quark_se_clock_control_off, - .get_rate = NULL, -}; - -int quark_se_clock_control_init(struct device *dev) -{ - LOG_DBG("Quark_SE clock controller on: %p", dev); - return 0; -} - -#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL - -static struct quark_se_clock_control_config clock_quark_se_peripheral_config = { - .base_address = CLOCK_PERIPHERAL_BASE_ADDR -}; - -DEVICE_AND_API_INIT(clock_quark_se_peripheral, - CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME, - &quark_se_clock_control_init, - NULL, &clock_quark_se_peripheral_config, - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - &quark_se_clock_control_api); - -#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL */ -#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL - -static struct quark_se_clock_control_config clock_quark_se_external_config = { - .base_address = CLOCK_EXTERNAL_BASE_ADDR -}; - -DEVICE_AND_API_INIT(clock_quark_se_external, - CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME, - &quark_se_clock_control_init, - NULL, &clock_quark_se_external_config, - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - &quark_se_clock_control_api); - -#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL */ -#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR - -static struct quark_se_clock_control_config clock_quark_se_sensor_config = { - .base_address = CLOCK_SENSOR_BASE_ADDR -}; - -DEVICE_AND_API_INIT(clock_quark_se_sensor, - CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME, - &quark_se_clock_control_init, - NULL, &clock_quark_se_sensor_config, - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - &quark_se_clock_control_api); - -#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR */ diff --git a/drivers/dma/dma_qmsi.c b/drivers/dma/dma_qmsi.c index 42a8c72037f..59de01bfb66 100644 --- a/drivers/dma/dma_qmsi.c +++ b/drivers/dma/dma_qmsi.c @@ -318,40 +318,6 @@ static void dma_qmsi_config(struct device *dev) irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1)); QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_1_mask); -#if (CONFIG_SOC_QUARK_SE_C1000) - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_2, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_2_mask); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_3, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_3_mask); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_4, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_4_mask); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_5, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_5_mask); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_6, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_6_mask); - - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7), CONFIG_DMA_0_IRQ_PRI, - qm_dma_0_isr_7, DEVICE_GET(dma_qmsi), 0); - irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7)); - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_7_mask); - -#endif /* CONFIG_SOC_QUARK_SE_C1000 */ - IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT), CONFIG_DMA_0_IRQ_PRI, qm_dma_0_error_isr, DEVICE_GET(dma_qmsi), 0); diff --git a/drivers/flash/soc_flash_qmsi.c b/drivers/flash/soc_flash_qmsi.c deleted file mode 100644 index 3bf7d33e05e..00000000000 --- a/drivers/flash/soc_flash_qmsi.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include -#include - -#include -#include -#include "flash_priv.h" - -#include "qm_flash.h" -#include "qm_soc_regs.h" - -struct soc_flash_data { -#ifdef CONFIG_SOC_FLASH_QMSI_API_REENTRANCY - struct k_sem sem; -#endif -#ifdef CONFIG_DEVICE_POWER_MANAGEMENT - u32_t device_power_state; - qm_flash_context_t saved_ctx[QM_FLASH_NUM]; -#endif -}; - -#define FLASH_HAS_CONTEXT_DATA \ - (CONFIG_SOC_FLASH_QMSI_API_REENTRANCY || CONFIG_DEVICE_POWER_MANAGEMENT) - -#if FLASH_HAS_CONTEXT_DATA -static struct soc_flash_data soc_flash_context; -#define FLASH_CONTEXT (&soc_flash_context) -#else -#define FLASH_CONTEXT (NULL) -#endif /* FLASH_HAS_CONTEXT_DATA */ - -#ifdef CONFIG_SOC_FLASH_QMSI_API_REENTRANCY -#define RP_GET(dev) (&((struct soc_flash_data *)(dev->driver_data))->sem) -#else -#define RP_GET(dev) (NULL) -#endif - -static inline bool is_aligned_32(u32_t data) -{ - return (data & 0x3) ? false : true; -} - -static qm_flash_region_t flash_region(u32_t addr) -{ - if ((addr >= QM_FLASH_REGION_SYS_0_BASE) && (addr < - (QM_FLASH_REGION_SYS_0_BASE + CONFIG_SOC_FLASH_QMSI_SYS_SIZE))) { - return QM_FLASH_REGION_SYS; - } - - /* invalid address */ - return QM_FLASH_REGION_NUM; -} - -static u32_t get_page_num(u32_t addr) -{ - switch (flash_region(addr)) { - case QM_FLASH_REGION_SYS: - return (addr - QM_FLASH_REGION_SYS_0_BASE) >> - QM_FLASH_PAGE_SIZE_BITS; - default: - /* invalid address */ - return 0xffffffff; - } -} - -static int flash_qmsi_read(struct device *dev, off_t addr, - void *data, size_t len) -{ - ARG_UNUSED(dev); - - if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) { - return -EINVAL; - } - - if (flash_region(addr) == QM_FLASH_REGION_NUM) { - /* starting address is not within flash */ - return -EIO; - } - - if (flash_region(addr + len - 4) == QM_FLASH_REGION_NUM) { - /* data area is not within flash */ - return -EIO; - } - - for (u32_t i = 0; i < (len >> 2); i++) { - UNALIGNED_PUT(sys_read32(addr + (i << 2)), - (u32_t *)data + i); - } - - return 0; -} - -static int flash_qmsi_write(struct device *dev, off_t addr, - const void *data, size_t len) -{ - qm_flash_t flash = QM_FLASH_0; - qm_flash_region_t reg; - u32_t data_word = 0U, offset = 0U, f_addr = 0U; - - if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) { - return -EINVAL; - } - - reg = flash_region(addr); - if (reg == QM_FLASH_REGION_NUM) { - return -EIO; - } - - if (flash_region(addr + len - 4) == QM_FLASH_REGION_NUM) { - return -EIO; - } - - for (u32_t i = 0; i < (len >> 2); i++) { - data_word = UNALIGNED_GET((u32_t *)data + i); - reg = flash_region(addr + (i << 2)); - f_addr = addr + (i << 2); - - switch (reg) { - case QM_FLASH_REGION_SYS: - offset = f_addr - QM_FLASH_REGION_SYS_0_BASE; - break; - default: - return -EIO; - } - -#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) - if (offset >= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> 1)) { - flash = QM_FLASH_1; - offset -= CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> 1; - } -#endif - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_take(RP_GET(dev), K_FOREVER); - } - - qm_flash_word_write(flash, reg, offset, data_word); - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_give(RP_GET(dev)); - } - } - - return 0; -} - -static int flash_qmsi_erase(struct device *dev, off_t addr, size_t size) -{ - qm_flash_t flash = QM_FLASH_0; - qm_flash_region_t reg; - u32_t page = 0U; - - /* starting address needs to be a 2KB aligned address */ - if (addr & QM_FLASH_ADDRESS_MASK) { - return -EINVAL; - } - - /* size needs to be multiple of 2KB */ - if (size & QM_FLASH_ADDRESS_MASK) { - return -EINVAL; - } - - reg = flash_region(addr); - if (reg == QM_FLASH_REGION_NUM) { - return -EIO; - } - - if (flash_region(addr + size - (QM_FLASH_PAGE_SIZE_DWORDS << 2)) == - QM_FLASH_REGION_NUM) { - return -EIO; - } - - for (u32_t i = 0; i < (size >> QM_FLASH_PAGE_SIZE_BITS); i++) { - page = get_page_num(addr) + i; -#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) - if (page >= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> - (QM_FLASH_PAGE_SIZE_BITS + 1))) { - flash = QM_FLASH_1; - page -= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> - (QM_FLASH_PAGE_SIZE_BITS + 1)); - } -#endif - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_take(RP_GET(dev), K_FOREVER); - } - - qm_flash_page_erase(flash, reg, page); - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_give(RP_GET(dev)); - } - } - - return 0; -} - -static int flash_qmsi_write_protection(struct device *dev, bool enable) -{ - qm_flash_config_t qm_cfg; - - qm_cfg.us_count = CONFIG_SOC_FLASH_QMSI_CLK_COUNT_US; - qm_cfg.wait_states = CONFIG_SOC_FLASH_QMSI_WAIT_STATES; - - if (enable) { - qm_cfg.write_disable = QM_FLASH_WRITE_DISABLE; - } else { - qm_cfg.write_disable = QM_FLASH_WRITE_ENABLE; - } - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_take(RP_GET(dev), K_FOREVER); - } - - qm_flash_set_config(QM_FLASH_0, &qm_cfg); - -#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) - qm_flash_set_config(QM_FLASH_1, &qm_cfg); -#endif - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_give(RP_GET(dev)); - } - - return 0; -} - -static const struct flash_driver_api flash_qmsi_api = { - .read = flash_qmsi_read, - .write = flash_qmsi_write, - .erase = flash_qmsi_erase, - .write_protection = flash_qmsi_write_protection, -#if defined(CONFIG_FLASH_PAGE_LAYOUT) - .page_layout = (flash_api_pages_layout) - flash_page_layout_not_implemented, -#endif - .write_block_size = 4, -}; - -#ifdef CONFIG_DEVICE_POWER_MANAGEMENT -static void flash_qmsi_set_power_state(struct device *dev, u32_t power_state) -{ - struct soc_flash_data *ctx = dev->driver_data; - - ctx->device_power_state = power_state; -} - -static u32_t flash_qmsi_get_power_state(struct device *dev) -{ - struct soc_flash_data *ctx = dev->driver_data; - - return ctx->device_power_state; -} - -static int flash_qmsi_suspend_device(struct device *dev) -{ - struct soc_flash_data *ctx = dev->driver_data; - qm_flash_t i; - - for (i = QM_FLASH_0; i < QM_FLASH_NUM; i++) { - qm_flash_save_context(i, &ctx->saved_ctx[i]); - } - flash_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE); - - return 0; -} - -static int flash_qmsi_resume_device(struct device *dev) -{ - struct soc_flash_data *ctx = dev->driver_data; - qm_flash_t i; - - for (i = QM_FLASH_0; i < QM_FLASH_NUM; i++) { - qm_flash_restore_context(i, &ctx->saved_ctx[i]); - } - flash_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE); - - return 0; -} - -static int flash_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command, - void *context, device_pm_cb cb, void *arg) -{ - int ret = 0; - - if (ctrl_command == DEVICE_PM_SET_POWER_STATE) { - if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) { - ret = flash_qmsi_suspend_device(dev); - } else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) { - ret = flash_qmsi_resume_device(dev); - } - } else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) { - *((u32_t *)context) = flash_qmsi_get_power_state(dev); - } - - if (cb) { - cb(dev, ret, context, arg); - } - - return ret; -} -#else -#define flash_qmsi_set_power_state(...) -#endif - -static int quark_flash_init(struct device *dev) -{ - qm_flash_config_t qm_cfg; - - qm_cfg.us_count = CONFIG_SOC_FLASH_QMSI_CLK_COUNT_US; - qm_cfg.wait_states = CONFIG_SOC_FLASH_QMSI_WAIT_STATES; - qm_cfg.write_disable = QM_FLASH_WRITE_ENABLE; - - qm_flash_set_config(QM_FLASH_0, &qm_cfg); - -#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) - qm_flash_set_config(QM_FLASH_1, &qm_cfg); -#endif - - if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) { - k_sem_init(RP_GET(dev), 1, UINT_MAX); - } - - flash_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE); - - return 0; -} - -DEVICE_DEFINE(quark_flash, CONFIG_SOC_FLASH_QMSI_DEV_NAME, quark_flash_init, - flash_qmsi_device_ctrl, FLASH_CONTEXT, NULL, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&flash_qmsi_api); diff --git a/drivers/gpio/gpio_dw.c b/drivers/gpio/gpio_dw.c index 6ff4ce97b7d..0eec0ffc210 100644 --- a/drivers/gpio/gpio_dw.c +++ b/drivers/gpio/gpio_dw.c @@ -113,22 +113,6 @@ static inline void gpio_dw_clock_off(struct device *port) #define gpio_dw_clock_off(...) #endif -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS -static inline void dw_set_both_edges(u32_t base_addr, u32_t pin) -{ - ARG_UNUSED(base_addr); - ARG_UNUSED(pin); -} -static inline int dw_base_to_block_base(u32_t base_addr) -{ - return base_addr; -} -static inline int dw_interrupt_support(const struct gpio_dw_config *config) -{ - ARG_UNUSED(config); - return 1; -} -#else static inline void dw_set_both_edges(u32_t base_addr, u32_t pin) { dw_set_bit(base_addr, INT_BOTHEDGE, pin, 1); @@ -146,7 +130,6 @@ static inline int dw_interrupt_support(const struct gpio_dw_config *config) { return ((int)(config->irq_num) > 0); } -#endif static inline void dw_interrupt_config(struct device *port, int access_op, u32_t pin, int flags) @@ -254,13 +237,8 @@ static inline int gpio_dw_read(struct device *port, int access_op, { struct gpio_dw_runtime *context = port->driver_data; u32_t base_addr = context->base_addr; -#ifndef CONFIG_SOC_QUARK_SE_C1000_SS u32_t ext_port = EXT_PORTA; -#endif -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS - *value = dw_read(base_addr, EXT_PORTA); -#else /* 4-port GPIO implementation translates from base address to port */ switch (dw_derive_port_from_base(base_addr)) { case 1: @@ -277,7 +255,6 @@ static inline int gpio_dw_read(struct device *port, int access_op, break; } *value = dw_read(dw_base_to_block_base(base_addr), ext_port); -#endif if (GPIO_ACCESS_BY_PIN == access_op) { *value = !!(*value & BIT(pin)); @@ -387,19 +364,7 @@ static int gpio_dw_device_ctrl(struct device *port, u32_t ctrl_command, #define gpio_dw_set_power_state(...) #endif -#if defined(CONFIG_SOC_QUARK_SE_C1000) -static inline void gpio_dw_unmask_int(u32_t mask_addr) -{ - sys_write32(sys_read32(mask_addr) & INT_UNMASK_IA, mask_addr); -} -#elif CONFIG_SOC_QUARK_SE_C1000_SS -static inline void gpio_dw_unmask_int(u32_t mask_addr) -{ - sys_write32(sys_read32(mask_addr) & INT_ENABLE_ARC, mask_addr); -} -#else #define gpio_dw_unmask_int(...) -#endif static void gpio_dw_isr(void *arg) { @@ -473,10 +438,6 @@ static int gpio_dw_initialize(struct device *port) if (dw_interrupt_support(config)) { base_addr = dw_base_to_block_base(context->base_addr); -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS - /* Need to enable clock for GPIO controller */ - dw_set_bit(base_addr, INT_CLOCK_SYNC, CLK_ENA_POS, 1); -#endif /* CONFIG_SOC_QUARK_SE_C1000_SS */ /* interrupts in sync with system clock */ dw_set_bit(base_addr, INT_CLOCK_SYNC, LS_SYNC_POS, 1); diff --git a/drivers/gpio/gpio_dw_registers.h b/drivers/gpio/gpio_dw_registers.h index 4eb6c79ccf1..e47b40d08f7 100644 --- a/drivers/gpio/gpio_dw_registers.h +++ b/drivers/gpio/gpio_dw_registers.h @@ -9,22 +9,6 @@ #ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ #define ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS -#define SWPORTA_DR 0x00 -#define SWPORTA_DDR 0x01 -#define INTEN 0x03 -#define INTMASK 0x04 -#define INTTYPE_LEVEL 0x05 -#define INT_POLARITY 0x06 -#define INTSTATUS 0x07 -#define PORTA_DEBOUNCE 0x08 -#define PORTA_EOI 0x09 -#define EXT_PORTA 0x0A -#define INT_CLOCK_SYNC 0x0B - -#define CLK_ENA_POS (31) - -#else /** This definition of GPIO related registers supports four ports: A, B, C, D * yet only PORTA supports interrupts and debounce. */ @@ -57,7 +41,6 @@ #define VER_ID_CODE 0x6c #define CONFIG_REG2 0x70 #define CONFIG_REG1 0x74 -#endif #define LS_SYNC_POS (0) diff --git a/drivers/ipm/CMakeLists.txt b/drivers/ipm/CMakeLists.txt index 7398bbb8619..86f5c8aeae8 100644 --- a/drivers/ipm/CMakeLists.txt +++ b/drivers/ipm/CMakeLists.txt @@ -4,7 +4,6 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_IPM_MCUX ipm_mcux.c) zephyr_library_sources_ifdef(CONFIG_IPM_IMX ipm_imx.c) -zephyr_library_sources_ifdef(CONFIG_IPM_QUARK_SE ipm_quark_se.c) zephyr_library_sources_ifdef(CONFIG_IPM_MHU ipm_mhu.c) zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c) diff --git a/drivers/ipm/Kconfig b/drivers/ipm/Kconfig index a86a80cffeb..ebf777962ab 100644 --- a/drivers/ipm/Kconfig +++ b/drivers/ipm/Kconfig @@ -6,20 +6,6 @@ menuconfig IPM Include interrupt-based inter-processor mailboxes drivers in system configuration -config IPM_QUARK_SE - bool "Quark SE IPM driver" - depends on IPM - help - Driver for Quark SE mailboxes - -config IPM_QUARK_SE_MASTER - bool "Quark SE IPM master controller" - depends on IPM_QUARK_SE - help - Enable this for the first CPU that initializes IPM. - Sets up the initial interrupt mask and clears out all - channels. Should be turned on for one CPU only. - config IPM_MCUX bool "MCUX IPM driver" depends on IPM && HAS_MCUX diff --git a/drivers/ipm/ipm_quark_se.c b/drivers/ipm/ipm_quark_se.c deleted file mode 100644 index 0c0c9a53ca0..00000000000 --- a/drivers/ipm/ipm_quark_se.c +++ /dev/null @@ -1,228 +0,0 @@ -/* ipm_quark_se.c - Quark SE mailbox driver */ - -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ipm_quark_se.h" - - -/* We have a single ISR for all channels, so in order to properly handle - * messages we need to figure out which device object corresponds to - * in incoming channel - */ -static struct device *device_by_channel[QUARK_SE_IPM_CHANNELS]; -static u32_t inbound_channels; -const struct ipm_driver_api ipm_quark_se_api_funcs; - -static u32_t quark_se_ipm_sts_get(void) -{ - return sys_read32(QUARK_SE_IPM_CHALL_STS) & inbound_channels; -} - -static void set_channel_irq_state(int channel, int enable) -{ - mem_addr_t addr = QUARK_SE_IPM_MASK; - int bit = channel + QUARK_SE_IPM_MASK_START_BIT; - - if (enable) { - sys_clear_bit(addr, bit); - } else { - sys_set_bit(addr, bit); - } -} - - -/* Interrupt handler, gets messages on all incoming enabled mailboxes */ -void quark_se_ipm_isr(void *param) -{ - int channel; - int sts, bit; - struct device *d; - const struct quark_se_ipm_config_info *config; - struct quark_se_ipm_driver_data *driver_data; - volatile struct quark_se_ipm *ipm; - unsigned int key; - - ARG_UNUSED(param); - - while ((sts = quark_se_ipm_sts_get())) { - __ASSERT(sts, "spurious IPM interrupt"); - bit = find_msb_set(sts) - 1; - channel = bit / 2; - d = device_by_channel[channel]; - - __ASSERT(d, "got IRQ on channel with no IPM device"); - config = d->config->config_info; - driver_data = d->driver_data; - ipm = config->ipm; - - __ASSERT(driver_data->callback, - "enabled IPM channel with no callback"); - driver_data->callback(driver_data->callback_ctx, - ipm->ctrl & QUARK_SE_IPM_CTRL_CTRL_MASK, - &ipm->data); - - key = irq_lock(); - - /* Clear the interrupt bit */ - ipm->sts = QUARK_SE_IPM_STS_IRQ_BIT; - /* Clear channel status bit */ - ipm->sts = QUARK_SE_IPM_STS_STS_BIT; - - /* Wait for the above register writes to clear the channel - * to propagate to the global channel status register - */ - while (quark_se_ipm_sts_get() & (0x3 << (channel * 2))) { - /* Busy-wait */ - } - irq_unlock(key); - } -} - -static int quark_se_ipm_send(struct device *d, int wait, u32_t id, - const void *data, int size) -{ - const struct quark_se_ipm_config_info *config = d->config->config_info; - volatile struct quark_se_ipm *ipm = config->ipm; - u32_t data32[4]; /* Until we change API to u32_t array */ - unsigned int flags; - int i; - - if (id > QUARK_SE_IPM_MAX_ID_VAL) { - return -EINVAL; - } - - if (config->direction != QUARK_SE_IPM_OUTBOUND) { - return -EINVAL; - } - - if (size > QUARK_SE_IPM_DATA_REGS * sizeof(u32_t)) { - return -EMSGSIZE; - } - - flags = irq_lock(); - - if (ipm->sts & QUARK_SE_IPM_STS_STS_BIT) { - irq_unlock(flags); - return -EBUSY; - } - - /* Actual message is passing using 32 bits registers */ - memcpy(data32, data, size); - - for (i = 0; i < ARRAY_SIZE(data32); ++i) { - ipm->data[i] = data32[i]; - } - - ipm->ctrl = id | QUARK_SE_IPM_CTRL_IRQ_BIT; - - /* Wait for HW to set the sts bit */ - while (!(ipm->sts & QUARK_SE_IPM_STS_STS_BIT)) { - } - - irq_unlock(flags); - - if (wait) { - /* Loop until remote clears the status bit */ - while (ipm->sts & QUARK_SE_IPM_STS_STS_BIT) { - } - } - - return 0; -} - - -static int quark_se_ipm_max_data_size_get(struct device *d) -{ - ARG_UNUSED(d); - - return QUARK_SE_IPM_DATA_REGS * sizeof(u32_t); -} - - -static u32_t quark_se_ipm_max_id_val_get(struct device *d) -{ - ARG_UNUSED(d); - - return QUARK_SE_IPM_MAX_ID_VAL; -} - -static void quark_se_ipm_register_callback(struct device *d, ipm_callback_t cb, - void *context) -{ - struct quark_se_ipm_driver_data *driver_data = d->driver_data; - - driver_data->callback = cb; - driver_data->callback_ctx = context; -} - - -static int quark_se_ipm_set_enabled(struct device *d, int enable) -{ - const struct quark_se_ipm_config_info *config_info = - d->config->config_info; - - if (config_info->direction != QUARK_SE_IPM_INBOUND) { - return -EINVAL; - } - set_channel_irq_state(config_info->channel, enable); - return 0; -} - -const struct ipm_driver_api ipm_quark_se_api_funcs = { - .send = quark_se_ipm_send, - .register_callback = quark_se_ipm_register_callback, - .max_data_size_get = quark_se_ipm_max_data_size_get, - .max_id_val_get = quark_se_ipm_max_id_val_get, - .set_enabled = quark_se_ipm_set_enabled -}; - -int quark_se_ipm_controller_initialize(struct device *d) -{ - const struct quark_se_ipm_controller_config_info *config = - d->config->config_info; -#if CONFIG_IPM_QUARK_SE_MASTER - int i; - - /* Mask all mailbox interrupts, we'll enable them - * individually later. Clear out any pending messages - */ - sys_write32(0xFFFFFFFF, QUARK_SE_IPM_MASK); - for (i = 0; i < QUARK_SE_IPM_CHANNELS; ++i) { - volatile struct quark_se_ipm *ipm = QUARK_SE_IPM(i); - - ipm->sts = 0U; - } -#endif - - if (config->controller_init) { - return config->controller_init(); - } - return 0; -} - - -int quark_se_ipm_initialize(struct device *d) -{ - const struct quark_se_ipm_config_info *config = d->config->config_info; - - device_by_channel[config->channel] = d; - if (config->direction == QUARK_SE_IPM_INBOUND) { - inbound_channels |= (0x3 << (config->channel * 2)); - } - - return 0; -} diff --git a/drivers/ipm/ipm_quark_se.h b/drivers/ipm/ipm_quark_se.h deleted file mode 100644 index 19f20936685..00000000000 --- a/drivers/ipm/ipm_quark_se.h +++ /dev/null @@ -1,131 +0,0 @@ -/* ipm_quark_se.h - Quark SE mailbox driver */ - -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef ZEPHYR_DRIVERS_IPM_IPM_QUARK_SE_H_ -#define ZEPHYR_DRIVERS_IPM_IPM_QUARK_SE_H_ - -#include -#include /* for SCSS_REGISTER_BASE */ -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define QUARK_SE_IPM_OUTBOUND 0 -#define QUARK_SE_IPM_INBOUND 1 - -#if defined(CONFIG_SOC_QUARK_SE_C1000) -/* First byte of the QUARK_SE_IPM_MASK register is for the Lakemont */ -#define QUARK_SE_IPM_MASK_START_BIT 0 -#define QUARK_SE_IPM_INTERRUPT 21 -#define QUARK_SE_IPM_ARC_LMT_DIR QUARK_SE_IPM_INBOUND -#define QUARK_SE_IPM_LMT_ARC_DIR QUARK_SE_IPM_OUTBOUND - -#elif defined(CONFIG_SOC_QUARK_SE_C1000_SS) -/* Second byte is for ARC */ -#define QUARK_SE_IPM_MASK_START_BIT 8 -#define QUARK_SE_IPM_INTERRUPT 57 -#define QUARK_SE_IPM_ARC_LMT_DIR QUARK_SE_IPM_OUTBOUND -#define QUARK_SE_IPM_LMT_ARC_DIR QUARK_SE_IPM_INBOUND - -#else -#error "Unsupported platform for ipm_quark_se driver" -#endif - -#define QUARK_SE_IPM_CHANNELS 8 -#define QUARK_SE_IPM_DATA_REGS 4 -#define QUARK_SE_IPM_MAX_ID_VAL 0x7FFFFFFF - -/* QUARK_SE EAS section 28.5.1.123 */ -#define QUARK_SE_IPM_CTRL_CTRL_MASK BIT_MASK(31) -#define QUARK_SE_IPM_CTRL_IRQ_BIT BIT(31) - -#define QUARK_SE_IPM_STS_STS_BIT BIT(0) -#define QUARK_SE_IPM_STS_IRQ_BIT BIT(1) - -struct __packed quark_se_ipm { - u32_t ctrl; - u32_t data[QUARK_SE_IPM_DATA_REGS]; /* contiguous 32-bit registers */ - u32_t sts; -}; - -/* Base address for mailboxes - * - * Layout: - * - * quark_se_ipm[8] - * QUARK_SE_IPM_CHALL_STS - */ -#define QUARK_SE_IPM_BASE (SCSS_REGISTER_BASE + 0xa00) - -/* 28.5.1.73 Host processor Interrupt routing mask 21 - * - * Bits Description - * 31:24 Mailbox SS Halt interrupt maskIUL - * 23:16 Mailbox Host Halt interrupt mask - * 15:8 Mailbox SS interrupt mask - * 7:0 Mailbox Host interrupt mask - */ -#define QUARK_SE_IPM_MASK (SCSS_REGISTER_BASE + 0x4a0) - -/* All status bits of the mailboxes - * - * Bits Description - * 31:16 Reserved - * 15:0 CHn_STS bits (sts/irq) for all channels - */ -#define QUARK_SE_IPM_CHALL_STS (SCSS_REGISTER_BASE + 0x0AC0) - -#define QUARK_SE_IPM(channel) ((volatile struct quark_se_ipm *)(QUARK_SE_IPM_BASE + \ - ((channel) * sizeof(struct quark_se_ipm)))) - -struct quark_se_ipm_controller_config_info { - int (*controller_init)(void); -}; - -struct quark_se_ipm_config_info { - int channel; - int direction; - volatile struct quark_se_ipm *ipm; -}; - - -struct quark_se_ipm_driver_data { - ipm_callback_t callback; - void *callback_ctx; -}; - -extern const struct ipm_driver_api ipm_quark_se_api_funcs; - -void quark_se_ipm_isr(void *param); - -int quark_se_ipm_initialize(struct device *d); -int quark_se_ipm_controller_initialize(struct device *d); - -#define QUARK_SE_IPM_DEFINE(name, ch, dir) \ - struct quark_se_ipm_config_info quark_se_ipm_config_##name = { \ - .ipm = QUARK_SE_IPM(ch), \ - .channel = ch, \ - .direction = dir \ - }; \ - struct quark_se_ipm_driver_data quark_se_ipm_runtime_##name; \ - DEVICE_AND_API_INIT(name, Z_STRINGIFY(name), quark_se_ipm_initialize, \ - &quark_se_ipm_runtime_##name, \ - &quark_se_ipm_config_##name, \ - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ - &ipm_quark_se_api_funcs) - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_DRIVERS_IPM_IPM_QUARK_SE_H_ */ diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index 0e34d87752d..65e24f8d608 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -557,7 +557,6 @@ void spi_config_0_irq(void) IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_0_IRQ); - z_spi_int_unmask(SPI_DW_PORT_0_INT_MASK); #else IRQ_CONNECT(DT_SPI_0_IRQ_RX_AVAIL, DT_SPI_0_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); @@ -570,9 +569,6 @@ void spi_config_0_irq(void) irq_enable(DT_SPI_0_IRQ_TX_REQ); irq_enable(DT_SPI_0_IRQ_ERR_INT); - z_spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK); #endif } #endif /* CONFIG_SPI_0 */ @@ -606,7 +602,6 @@ void spi_config_1_irq(void) IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_1_IRQ); - z_spi_int_unmask(SPI_DW_PORT_1_INT_MASK); #else IRQ_CONNECT(DT_SPI_1_IRQ_RX_AVAIL, DT_SPI_1_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); @@ -619,9 +614,6 @@ void spi_config_1_irq(void) irq_enable(DT_SPI_1_IRQ_TX_REQ); irq_enable(DT_SPI_1_IRQ_ERR_INT); - z_spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK); #endif } #endif /* CONFIG_SPI_1 */ @@ -655,7 +647,6 @@ void spi_config_2_irq(void) IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_2_IRQ); - z_spi_int_unmask(SPI_DW_PORT_2_INT_MASK); #else IRQ_CONNECT(DT_SPI_2_IRQ_RX_AVAIL, DT_SPI_2_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); @@ -668,9 +659,6 @@ void spi_config_2_irq(void) irq_enable(DT_SPI_2_IRQ_TX_REQ); irq_enable(DT_SPI_2_IRQ_ERR_INT); - z_spi_int_unmask(SPI_DW_PORT_2_RX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_2_TX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_2_ERROR_INT_MASK); #endif } #endif /* CONFIG_SPI_2 */ @@ -704,7 +692,6 @@ void spi_config_3_irq(void) IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_3_IRQ); - z_spi_int_unmask(SPI_DW_PORT_3_INT_MASK); #else IRQ_CONNECT(DT_SPI_3_IRQ_RX_AVAIL, DT_SPI_3_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); @@ -717,9 +704,6 @@ void spi_config_3_irq(void) irq_enable(DT_SPI_3_IRQ_TX_REQ); irq_enable(DT_SPI_3_IRQ_ERR_INT); - z_spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK); - z_spi_int_unmask(SPI_DW_PORT_3_ERROR_INT_MASK); #endif } #endif /* CONFIG_SPI_3 */ diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index 9746c2b6e96..15f6d34324a 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -195,32 +195,11 @@ struct spi_dw_data { * Including the right register definition file * SoC SPECIFIC! */ -#ifdef CONFIG_SOC_QUARK_SE_C1000_SS -#include "spi_dw_quark_se_ss_regs.h" -#else #include "spi_dw_regs.h" #define z_extra_clock_on(...) #define z_extra_clock_off(...) -#endif - -/* Interrupt mask - * SoC SPECIFIC! - */ -#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) -#ifdef CONFIG_ARC -#define _INT_UNMASK INT_ENABLE_ARC -#else -#define _INT_UNMASK INT_UNMASK_IA -#endif - -#define z_spi_int_unmask(__mask) \ - sys_write32(sys_read32(__mask) & _INT_UNMASK, __mask) -#else -#define z_spi_int_unmask(...) -#endif /* CONFIG_SOC_QUARK_SE_C1000 || CONFIG_SOC_QUARK_SE_C1000_SS */ - /* Based on those macros above, here are common helpers for some registers */ DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16) DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32) diff --git a/drivers/spi/spi_dw_quark_se_ss_regs.h b/drivers/spi/spi_dw_quark_se_ss_regs.h deleted file mode 100644 index b74fa70c766..00000000000 --- a/drivers/spi/spi_dw_quark_se_ss_regs.h +++ /dev/null @@ -1,153 +0,0 @@ -/* spi_dw_quark_se_ss.h - Designware SPI driver private definitions */ - -/* - * Copyright (c) 2015 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_SPI_SPI_DW_QUARK_SE_SS_REGS_H_ -#define ZEPHYR_DRIVERS_SPI_SPI_DW_QUARK_SE_SS_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Registers: - * Some registers have been collapsed into one - * - SER is part of SSIENR - * - TXFTLR is part of RXFTLR - * This requires a little bit different access functions - * see below: write_ser(), write_rxftlr() and write_txftlr() - */ -#define DW_SPI_REG_CTRLR0 (0x00) -#define DW_SPI_REG_SSIENR (0x02) -#define DW_SPI_REG_BAUDR (0x04) -#define DW_SPI_REG_RXFTLR (0x05) -#define DW_SPI_REG_TXFLR (0x07) -#define DW_SPI_REG_RXFLR (0x08) -#define DW_SPI_REG_SR (0x09) -#define DW_SPI_REG_ISR (0x0a) -#define DW_SPI_REG_IMR (0x0b) -#define DW_SPI_REG_ICR (0x0c) -#define DW_SPI_REG_DR (0x0d) - -#define DW_SPI_CTRLR0_CLK_ENA_BIT (15) -#define DW_SPI_CTRLR0_CLK_ENA_MASK BIT(DW_SPI_CTRLR0_CLK_ENA_BIT) -#define DW_SPI_QSS_SSIENR_SER(__slv) (__slv << 4) -#define DW_SPI_QSS_TXFTLR(__lvl) (__lvl << 16) - -#define DW_SPI_QSS_SER_MASK (0xf0) -#define DW_SPI_QSS_RXFTLR_MASK (0x0000ffff) -#define DW_SPI_QSS_TXFTLR_MASK (0xffff0000) - -#define DW_SPI_DR_WD_BIT (30) -#define DW_SPI_DR_WD_MASK BIT(DW_SPI_DR_WD_BIT) -#define DW_SPI_DR_STROBE_BIT (31) -#define DW_SPI_DR_STROBE_MASK BIT(DW_SPI_DR_STROBE_BIT) - -#define DW_SPI_DR_WRITE (DW_SPI_DR_STROBE_MASK | \ - DW_SPI_DR_WD_MASK) -#define DW_SPI_DR_READ (DW_SPI_DR_STROBE_MASK) - -/* Register helpers - * *_b functions only used for creating proper ser one - */ - -/* CTRLR0 on Quark SE SS has a CLK_ENA bit we want to keep - * as it is while writing the configuration. - * *_b function only used for creating proper ser one - */ -DEFINE_MM_REG_READ(ctrlr0_b, DW_SPI_REG_CTRLR0, 16) -static inline u32_t read_ctrlr0(u32_t addr) -{ - return read_ctrlr0_b(addr); -} - -DEFINE_MM_REG_WRITE(ctrlr0_b, DW_SPI_REG_CTRLR0, 16) -static inline void write_ctrlr0(u32_t data, u32_t addr) -{ - write_ctrlr0_b((read_ctrlr0_b(addr) & DW_SPI_CTRLR0_CLK_ENA_MASK) | - data, addr); -} - -DEFINE_MM_REG_READ(ctrlr1_b, DW_SPI_REG_CTRLR0, 32) -DEFINE_MM_REG_WRITE(ctrlr1_b, DW_SPI_REG_CTRLR0, 32) -static inline void write_ctrlr1(u32_t data, u32_t addr) -{ - write_ctrlr1_b((read_ctrlr1_b(addr) & (data << 16)), addr); -} - -DEFINE_MM_REG_READ(ssienr_b, DW_SPI_REG_SSIENR, 8) -DEFINE_MM_REG_WRITE(ssienr_b, DW_SPI_REG_SSIENR, 8) -static inline void write_ser(u32_t data, u32_t addr) -{ - write_ssienr_b((read_ssienr_b(addr) & (~DW_SPI_QSS_SER_MASK)) | - DW_SPI_QSS_SSIENR_SER(data), addr); -} - -DEFINE_MM_REG_READ(rxftlr_b, DW_SPI_REG_RXFTLR, 32) -DEFINE_MM_REG_WRITE(rxftlr_b, DW_SPI_REG_RXFTLR, 32) -DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 16) - -static inline void write_rxftlr(u32_t data, u32_t addr) -{ - write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_RXFTLR_MASK)) | - data, addr); -} - -static inline void write_txftlr(u32_t data, u32_t addr) -{ - write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_TXFTLR_MASK)) | - DW_SPI_QSS_TXFTLR(data), addr); -} - -/* Quark SE SS requires to clear up all interrupts */ -DEFINE_MM_REG_WRITE(icr, DW_SPI_REG_ICR, 8) -static inline void clear_interrupts(u32_t addr) -{ - write_icr(0x1f, addr); -} - -/* Reading and Writing Data - * Quark SE SS DW SPI controller requires more logic from the driver which: - * - needs to tell when it has been pushing in bits for TX FIFO - * - needs to tell when it will be pulling out bits from RX FIFO - */ -DEFINE_MM_REG_WRITE(dr_b, DW_SPI_REG_DR, 32) -DEFINE_MM_REG_READ(dr_b, DW_SPI_REG_DR, 32) -static inline void write_dr(u32_t data, u32_t addr) -{ - write_dr_b(data | DW_SPI_DR_WRITE, addr); -} - -static inline u32_t read_dr(u32_t addr) -{ - write_dr_b(DW_SPI_DR_READ, addr); - __asm__("nop\n"); - return read_dr_b(addr); -} - -/* Internal clock gating */ -DEFINE_SET_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT) -DEFINE_CLEAR_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT) - -static inline void extra_clock_on(struct device *dev) -{ - const struct spi_dw_config *info = dev->config->config_info; - - set_bit_clk_ena(info->regs); -} - -static inline void extra_clock_off(struct device *dev) -{ - const struct spi_dw_config *info = dev->config->config_info; - - clear_bit_clk_ena(info->regs); -} - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_DRIVERS_SPI_SPI_DW_QUARK_SE_SS_REGS_H_ */ diff --git a/drivers/usb/device/usb_dc_dw.c b/drivers/usb/device/usb_dc_dw.c index 2e5f2431b8e..112516f25ec 100644 --- a/drivers/usb/device/usb_dc_dw.c +++ b/drivers/usb/device/usb_dc_dw.c @@ -64,13 +64,6 @@ struct usb_dw_ctrl_prv { static struct usb_dw_ctrl_prv usb_dw_ctrl; -static inline void usb_dw_int_unmask(void) -{ -#if defined(CONFIG_SOC_QUARK_SE_C1000) - QM_INTERRUPT_ROUTER->usb_0_int_mask &= ~BIT(0); -#endif -} - static void usb_dw_reg_dump(void) { u8_t i; @@ -172,36 +165,6 @@ static int usb_dw_reset(void) return 0; } -static int usb_dw_clock_enable(void) -{ -#if defined(CONFIG_SOC_QUARK_SE_C1000) - /* 7.2.7 USB Clock Operation */ - clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1); - - /* Enable the USB Clock */ - QM_SCSS_CCU->ccu_mlayer_ahb_ctl |= QM_CCU_USB_CLK_EN; - - /* Set up the PLL. */ - QM_USB_PLL_CFG0 = QM_USB_PLL_CFG0_DEFAULT | QM_USB_PLL_PDLD; - - /* Wait for the PLL lock */ - while (0 == (QM_USB_PLL_CFG0 & QM_USB_PLL_LOCK)) { - } -#endif - return 0; -} - -static void usb_dw_clock_disable(void) -{ -#if defined(CONFIG_SOC_QUARK_SE_C1000) - /* Disable the USB Clock */ - QM_SCSS_CCU->ccu_mlayer_ahb_ctl &= ~QM_CCU_USB_CLK_EN; - - /* Disable the PLL */ - QM_USB_PLL_CFG0 &= ~QM_USB_PLL_PDLD; -#endif -} - static int usb_dw_num_dev_eps(void) { return (USB_DW->ghwcfg2 >> 10) & 0xf; @@ -737,11 +700,6 @@ int usb_dc_attach(void) return 0; } - ret = usb_dw_clock_enable(); - if (ret) { - return ret; - } - ret = usb_dw_init(); if (ret) { return ret; @@ -752,8 +710,6 @@ int usb_dc_attach(void) usb_dw_isr_handler, 0, IOAPIC_EDGE | IOAPIC_HIGH); irq_enable(USB_DW_IRQ); - usb_dw_int_unmask(); - usb_dw_ctrl.attached = 1U; return 0; @@ -765,8 +721,6 @@ int usb_dc_detach(void) return 0; } - usb_dw_clock_disable(); - irq_disable(USB_DW_IRQ); /* Enable soft disconnect */ diff --git a/drivers/usb/device/usb_dw_registers.h b/drivers/usb/device/usb_dw_registers.h index c43ac8a8e53..1a77da5158a 100644 --- a/drivers/usb/device/usb_dw_registers.h +++ b/drivers/usb/device/usb_dw_registers.h @@ -17,10 +17,6 @@ #include -#if defined(CONFIG_SOC_QUARK_SE_C1000) -#include "qm_soc_regs.h" -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/dts/arc/quark_se_c1000_ss.dtsi b/dts/arc/quark_se_c1000_ss.dtsi deleted file mode 100644 index 999230ff7b1..00000000000 --- a/dts/arc/quark_se_c1000_ss.dtsi +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "skeleton.dtsi" - -#include -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "snps,arcem4"; - reg = <1>; - }; - - core_intc: arcv2-intc { - compatible = "snps,arcv2-intc"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - flash0: flash@DT_FLASH_ADDR { - compatible = "soc-nv-flash"; - reg = ; - }; - - sram0: memory@a8000400 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0xa8000400 DT_SRAM_SIZE>; - }; - - dccm0: dccm@80000000 { - device_type = "memory"; - compatible = "arc,dccm"; - reg = <0x80000000 DT_DCCM_SIZE>; - }; - - sysclk: system-clock { - compatible = "fixed-clock"; - clock-frequency = <32000000>; - #clock-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - rtc: rtc@b0000400 { - compatible = "intel,qmsi-rtc"; - reg = <0xb0000400 0x400>; - clock-frequency = <32768>; - interrupts = <47 1>; - interrupt-parent = <&core_intc>; - label = "RTC_0"; - }; - - uart0: uart@b0002000 { - compatible = "intel,qmsi-uart"; - reg = <0xb0002000 0x400>; - interrupts = <41 0>; - interrupt-parent = <&core_intc>; - clocks = <&sysclk>; - label = "UART_0"; - - status = "disabled"; - }; - - uart1: uart@b0002400 { - compatible = "intel,qmsi-uart"; - reg = <0xb0002400 0x400>; - interrupts = <42 0>; - interrupt-parent = <&core_intc>; - clocks = <&sysclk>; - label = "UART_1"; - - status = "disabled"; - }; - - gpio0: gpio@80017800 { - compatible = "intel,qmsi-ss-gpio"; - reg = <0x80017800 0x100>; - interrupts = <20 1>; - interrupt-parent = <&core_intc>; - label = "GPIO_0"; - - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: gpio@80017900 { - compatible = "intel,qmsi-ss-gpio"; - reg = <0x80017900 0x100>; - interrupts = <21 1>; - interrupt-parent = <&core_intc>; - label = "GPIO_1"; - - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: gpio@b0000c00 { - compatible = "intel,qmsi-gpio"; - reg = <0xb0000c00 0x400>; - interrupts = <44 1>; - interrupt-parent = <&core_intc>; - label = "GPIO_2"; - - gpio-controller; - #gpio-cells = <2>; - }; - - gpio3: gpio@b0800b00 { - compatible = "intel,qmsi-gpio"; - reg = <0xb0800b00 0x400>; - interrupts = <67 1>; - interrupt-parent = <&core_intc>; - label = "GPIO_3"; - - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@80012000 { - compatible = "intel,qmsi-ss-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80012000 0x100>; - interrupts = <22 1>, <25 1>, <24 1>, <23 1>; - interrupt-names = "error", "stop", "tx", "rx"; - interrupt-parent = <&core_intc>; - label = "I2C_0"; - - status = "disabled"; - }; - - i2c1: i2c@80012100 { - compatible = "intel,qmsi-ss-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80012100 0x100>; - interrupts = <26 1>, <29 1>, <28 1>, <27 1>; - interrupt-names = "error", "stop", "tx", "rx"; - interrupt-parent = <&core_intc>; - label = "I2C_1"; - - status = "disabled"; - }; - - i2c2: i2c@b0002800 { - compatible = "intel,qmsi-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0002800 0x400>; - interrupts = <36 1>; - interrupt-parent = <&core_intc>; - label = "I2C_2"; - - status = "disabled"; - }; - - i2c3: i2c@b0002c00 { - compatible = "intel,qmsi-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0002c00 0x400>; - interrupts = <37 1>; - interrupt-parent = <&core_intc>; - label = "I2C_3"; - - status = "disabled"; - }; - - spi0: spi@80010000 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80010000 0x400>; - clocks = <&sysclk>; - interrupts = <30 2>, <31 2>, <32 2>; - interrupt-names = "err-int", "rx-avail", "tx-req"; - interrupt-parent = <&core_intc>; - label = "SPI_0"; - status = "disabled"; - }; - - spi1: spi@80010100 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80010100 0x400>; - clocks = <&sysclk>; - interrupts = <33 2>, <34 2>, <35 2>; - interrupt-names = "err-int", "rx-avail", "tx-req"; - interrupt-parent = <&core_intc>; - label = "SPI_1"; - status = "disabled"; - }; - - adc0: adc@80015000 { - compatible = "snps,dw-adc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80015000 0x05>; - interrupts = <19 0>, <18 0>; - interrupt-names = "normal", "error"; - interrupt-parent = <&core_intc>; - label = "ADC_0"; - - status = "disabled"; - }; - - wdog0: watchdog@b0000000 { - compatible = "intel,qmsi-watchdog"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0000000 0x400>; - interrupts = <48 0>; - interrupt-parent = <&core_intc>; - - label = "WATCHDOG_0"; - }; - }; -}; diff --git a/dts/x86/intel_curie.dtsi b/dts/x86/intel_curie.dtsi deleted file mode 100644 index f600c06cbf0..00000000000 --- a/dts/x86/intel_curie.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "skeleton.dtsi" -#include -#include -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "intel,quark"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arc"; - reg = <1>; - }; - }; - - flash0: flash@40010000 { - compatible = "soc-nv-flash"; - reg = <0x40010000 DT_FLASH_SIZE>; - }; - - flash1: flash@40030000 { - compatible = "soc-nv-flash"; - reg = <0x40030000 DT_FLASH_SIZE>; - }; - - sram0: memory@a8007000 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0xa8007000 DT_SRAM_SIZE>; - }; - - intc: ioapic@fec00000 { - compatible = "intel,ioapic"; - reg = <0xfec00000 0x1000>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - sysclk: system-clock { - compatible = "fixed-clock"; - clock-frequency = <32000000>; - #clock-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - rtc: rtc@b0000400 { - compatible = "intel,qmsi-rtc"; - reg = <0xb0000400 0x400>; - clock-frequency = <32768>; - interrupts = <11 IRQ_TYPE_EDGE_RISING 2>; - interrupt-parent = <&intc>; - label = "RTC_0"; - }; - - uart0: uart@b0002000 { - compatible = "intel,qmsi-uart"; - reg = <0xb0002000 0x400>; - label = "UART_0"; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>; - interrupt-parent = <&intc>; - clocks = <&sysclk>; - - status = "disabled"; - }; - - uart1: uart@b0002400 { - compatible = "intel,qmsi-uart"; - reg = <0xb0002400 0x400>; - label = "UART_1"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 3>; - interrupt-parent = <&intc>; - clocks = <&sysclk>; - - status = "disabled"; - }; - - gpio0: gpio@b0000c00 { - compatible = "intel,qmsi-gpio"; - reg = <0xb0000c00 0x400>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "GPIO_0"; - - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: gpio@b0800b00 { - compatible = "intel,qmsi-gpio"; - reg = <0xb0800b00 0x400>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "GPIO_1"; - - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@b0002800 { - compatible = "intel,qmsi-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0002800 0x400>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "I2C_0"; - - status = "disabled"; - }; - - i2c1: i2c@b0002c00 { - compatible = "intel,qmsi-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0002c00 0x400>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "I2C_1"; - - status = "disabled"; - }; - - spi0: spi@b0001000 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0001000 0x400>; - clocks = <&sysclk>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "SPI_0"; - status = "disabled"; - }; - - spi1: spi@b0001400 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0001400 0x400>; - clocks = <&sysclk>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "SPI_1"; - status = "disabled"; - }; - - spi2: spi@b0001800 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xb0001800 0x400>; - clocks = <&sysclk>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 2>; - interrupt-parent = <&intc>; - label = "SPI_2"; - status = "disabled"; - }; - - wdog0: watchdog@b0000000 { - compatible = "intel,qmsi-watchdog"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0xb0000000 0x400>; - interrupts = <12 IRQ_TYPE_EDGE_RISING 2>; - interrupt-parent = <&intc>; - - label = "WATCHDOG_0"; - - }; - }; -}; diff --git a/include/aio_comparator.h b/include/aio_comparator.h deleted file mode 100644 index 87311d6f97d..00000000000 --- a/include/aio_comparator.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ZEPHYR_INCLUDE_AIO_COMPARATOR_H_ -#define ZEPHYR_INCLUDE_AIO_COMPARATOR_H_ - -#ifndef CONFIG_COMPAT_INCLUDES -#warning "This header file has moved, include instead." -#endif - -#include - -#endif /* ZEPHYR_INCLUDE_AIO_COMPARATOR_H_ */ diff --git a/include/drivers/aio_comparator.h b/include/drivers/aio_comparator.h deleted file mode 100644 index 92214914ef5..00000000000 --- a/include/drivers/aio_comparator.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DRIVERS_AIO_COMPARATOR_H_ -#define ZEPHYR_INCLUDE_DRIVERS_AIO_COMPARATOR_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -enum aio_cmp_ref { - AIO_CMP_REF_A, /**< Use reference A. */ - AIO_CMP_REF_B, /**< Use reference B. */ -}; - -enum aio_cmp_polarity { - AIO_CMP_POL_RISE, /**< Match on rising edge. */ - AIO_CMP_POL_FALL, /**< Match on falling edge. */ -}; - -typedef void (*aio_cmp_cb)(void *); - -typedef int (*aio_cmp_api_disable)(struct device *dev, u8_t index); - -typedef int (*aio_cmp_api_configure)(struct device *dev, u8_t index, - enum aio_cmp_polarity polarity, enum aio_cmp_ref refsel, - aio_cmp_cb cb, void *param); -typedef u32_t (*aio_cmp_api_get_pending_int)(struct device *dev); - -struct aio_cmp_driver_api { - aio_cmp_api_disable disable; - aio_cmp_api_configure configure; - aio_cmp_api_get_pending_int get_pending_int; -}; - -/** - * @brief Disable a particular comparator. - * - * This disables a comparator so that it no longer triggers interrupts. - * - * @param dev Device struct - * @param index The index of the comparator to disable - * - * @return 0 if successful, otherwise failed. - */ -__syscall int aio_cmp_disable(struct device *dev, u8_t index); - -static inline int z_impl_aio_cmp_disable(struct device *dev, u8_t index) -{ - const struct aio_cmp_driver_api *api = dev->driver_api; - - return api->disable(dev, index); -} - -/** - * @brief Configure and enable a particular comparator. - * - * This performs configuration and enable a comparator, so that it will - * generate interrupts when conditions are met. - * - * @param dev Device struct - * @param index The index of the comparator to disable - * @param polarity Match polarity (e.g. rising or falling) - * @param refsel Reference for trigger - * @param cb Function callback (aio_cmp_cb) - * @param param Parameters to be passed to callback - * - * @return 0 if successful, otherwise failed. - */ -static inline int aio_cmp_configure(struct device *dev, u8_t index, - enum aio_cmp_polarity polarity, - enum aio_cmp_ref refsel, - aio_cmp_cb cb, void *param) -{ - const struct aio_cmp_driver_api *api = dev->driver_api; - - return api->configure(dev, index, polarity, refsel, cb, param); -} - -/** - * @brief Function to get pending interrupts - * - * The purpose of this function is to return the interrupt - * status register for the device. - * This is especially useful when waking up from - * low power states to check the wake up source. - * - * @param dev Pointer to the device structure for the driver instance. - * - * @retval status != 0 if at least one aio_cmp interrupt is pending. - * @retval 0 if no aio_cmp interrupt is pending. - */ -__syscall int aio_cmp_get_pending_int(struct device *dev); - -static inline int z_impl_aio_cmp_get_pending_int(struct device *dev) -{ - struct aio_cmp_driver_api *api; - - api = (struct aio_cmp_driver_api *)dev->driver_api; - return api->get_pending_int(dev); -} - -#ifdef __cplusplus -} -#endif - -#include - -#endif /* ZEPHYR_INCLUDE_DRIVERS_AIO_COMPARATOR_H_ */ diff --git a/include/drivers/clock_control/quark_se_clock_control.h b/include/drivers/clock_control/quark_se_clock_control.h deleted file mode 100644 index f6b4a0274db..00000000000 --- a/include/drivers/clock_control/quark_se_clock_control.h +++ /dev/null @@ -1,54 +0,0 @@ -/* quark_se_clock_control.h - Clock controller header for Quark SE */ - -/* - * Copyright (c) 2015 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_ -#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_ - -enum quark_se_peripheral_clocks { - QUARK_SE_PERIPH_PCLK_EN = 0, - QUARK_SE_CCU_PERIPH_PCLK_EN, - QUARK_SE_CCU_I2C_M0_PCLK_EN, - QUARK_SE_CCU_I2C_M1_PCLK_EN, - QUARK_SE_CCU_SPI_S_PCLK_EN, - QUARK_SE_CCU_SPI_M0_PCLK_EN, - QUARK_SE_CCU_SPI_M1_PCLK_EN, - QUARK_SE_CCU_GPIO_INTR_PCLK_EN, - QUARK_SE_CCU_PERIPH_GPIO_DB_PCLK_EN, - QUARK_SE_CCU_I2S_PCLK_EN, - QUARK_SE_CCU_WDT_PCLK_EN_SW, - QUARK_SE_CCU_RTC_PCLK_EN_SW, - QUARK_SE_CCU_PWM_PCLK_EN_SW, - QUARK_SE_CCU_GPIO_PCLK_EN_SW, - QUARK_SE_CCU_SPI_M0_PCLK_EN_SW, - QUARK_SE_CCU_SPI_M1_PCLK_EN_SW, - QUARK_SE_CCU_SPI_PCLK_EN_SW, - QUARK_SE_CCU_UARTA_PCLK_EN_SW, - QUARK_SE_CCU_UARTB_PCLK_EN_SW, - QUARK_SE_CCU_I2C_M0_PCLK_EN_SW, - QUARK_SE_CCU_I2C_M1_PCLK_EN_SW, - QUARK_SE_CCU_I2S_PCLK_EN_SW, -}; - -enum quark_se_external_clocks { - QUARK_SE_CCU_EXT_RTC_EN = 0, - QUARK_SE_CCU_EXT_CLK_EN, - QUARK_SE_CCU_EXT_CLK_DIV_EN, -}; - -enum quark_se_sensor_clocks { - QUARK_SE_CCU_SENSOR_CLK_EN = 0, - QUARK_SE_CCU_SS_I2C_M0_CLK_EN, - QUARK_SE_CCU_SS_I2C_M1_CLK_EN, - QUARK_SE_CCU_SS_SPI_M0_CLK_EN, - QUARK_SE_CCU_SS_SPI_M1_CLK_EN, - QUARK_SE_CCU_SS_GPIO_INTR_CLK_EN, - QUARK_SE_CCU_SS_GPIO_DB_CLK_EN, - QUARK_SE_CCU_ADC_CLK_EN, -}; - -#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_ */ diff --git a/samples/net/sockets/echo_client/arduino_101.overlay b/samples/net/sockets/echo_client/arduino_101.overlay deleted file mode 100644 index 7a5b81d11f8..00000000000 --- a/samples/net/sockets/echo_client/arduino_101.overlay +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2018-2019 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&spi1 { - status = "okay"; - cs-gpios = <&gpio0 0 0>; - - enc28j60@0 { - compatible = "microchip,enc28j60"; - spi-port-name = "SPI_1"; - local-mac-address = [00 00 00 00 00 00]; - spi-max-frequency = <128000>; - int-gpios = <&gpio0 19 1>; - status = "okay"; - label = "ETH_0"; - reg = <0>; - }; -}; diff --git a/samples/net/wifi/quark_se_c1000_devboard.overlay b/samples/net/wifi/quark_se_c1000_devboard.overlay deleted file mode 100644 index d3c7914d17f..00000000000 --- a/samples/net/wifi/quark_se_c1000_devboard.overlay +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - - -&spi1 { - status = "okay"; - - cs-gpios = <&gpio0 13 0>; - - winc1500@0 { - status = "okay"; - compatible = "atmel,winc1500"; - reg = <0x0>; - label = "winc1500"; - spi-max-frequency = <8000000>; - irq-gpios = <&gpio0 18 0>; - reset-gpios = <&gpio0 26 0>; - enable-gpios = <&gpio0 19 0>; - - }; -}; diff --git a/samples/net/wpan_serial/sample.yaml b/samples/net/wpan_serial/sample.yaml index 4d44d057929..989e128e819 100644 --- a/samples/net/wpan_serial/sample.yaml +++ b/samples/net/wpan_serial/sample.yaml @@ -5,5 +5,5 @@ tests: sample.net.wpan.serial: harness: net depends_on: usb_device - platform_whitelist: quark_se_c1000_devboard tags: usb + skip: true # Needs to be adapted to another board with 15.4 diff --git a/samples/net/wpanusb/README.rst b/samples/net/wpanusb/README.rst index f3f28bf336d..abc4c9b843d 100644 --- a/samples/net/wpanusb/README.rst +++ b/samples/net/wpanusb/README.rst @@ -49,16 +49,6 @@ Example building for the Nordic nRF52840 Development Kit: :goals: run :compact: -Example building for the Quark SE C1000 Devboard with TI CC2520 support: - -.. zephyr-app-commands:: - :zephyr-app: samples/net/wpanusb - :host-os: unix - :board: quark_se_c1000_devboard - :conf: "prj.conf overlay-cc2520.conf" - :goals: run - :compact: - When connected to Linux with wpanusb kernel driver, it is recognized as: .. code-block:: console diff --git a/samples/net/wpanusb/overlay-cc2520.conf b/samples/net/wpanusb/overlay-cc2520.conf deleted file mode 100644 index ad7f6e99157..00000000000 --- a/samples/net/wpanusb/overlay-cc2520.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_IEEE802154_CC2520=y -CONFIG_NET_CONFIG_IEEE802154_DEV_NAME="cc2520" diff --git a/samples/net/wpanusb/sample.yaml b/samples/net/wpanusb/sample.yaml index 8b6035cecfa..a71bb6f7e6c 100644 --- a/samples/net/wpanusb/sample.yaml +++ b/samples/net/wpanusb/sample.yaml @@ -8,6 +8,3 @@ tests: sample.net.wpanusb_frdm_cr20a: extra_args: SHIELD=frdm_cr20a platform_whitelist: frdm_k64f - sample.net.wpanusb_quark_se_cc2520: - extra_args: OVERLAY_CONFIG=overlay-cc2520.conf - platform_whitelist: quark_se_c1000_devboard diff --git a/samples/net/zperf/boards/quark_se_c1000_devboard.conf b/samples/net/zperf/boards/quark_se_c1000_devboard.conf deleted file mode 100644 index 842cf4ebb87..00000000000 --- a/samples/net/zperf/boards/quark_se_c1000_devboard.conf +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_NET_L2_IEEE802154=y -CONFIG_IEEE802154_CC2520=y -CONFIG_NET_6LO_CONTEXT=y - -CONFIG_NET_PKT_RX_COUNT=24 -CONFIG_NET_PKT_TX_COUNT=24 -CONFIG_NET_BUF_RX_COUNT=48 -CONFIG_NET_BUF_TX_COUNT=48 -CONFIG_NET_BUF_DATA_SIZE=128 - -CONFIG_SHELL_CMDS_RESIZE=n diff --git a/samples/sensor/bme280/arduino_101_sss.overlay b/samples/sensor/bme280/arduino_101_sss.overlay deleted file mode 100644 index 7f1b3ec7d85..00000000000 --- a/samples/sensor/bme280/arduino_101_sss.overlay +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2019 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&i2c0 { - bme280@76 { - compatible = "bosch,bme280"; - reg = <0x76>; - label = "BME280"; - }; -}; diff --git a/samples/subsys/ipc/ipm_mailbox/ap/CMakeLists.txt b/samples/subsys/ipc/ipm_mailbox/ap/CMakeLists.txt deleted file mode 100644 index 11305d369c6..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/ap/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(ipm_mailbox_ap) - -target_include_directories(app PRIVATE $ENV{ZEPHYR_BASE}/drivers) -target_sources(app PRIVATE src/hello.c) diff --git a/samples/subsys/ipc/ipm_mailbox/ap/prj.conf b/samples/subsys/ipc/ipm_mailbox/ap/prj.conf deleted file mode 100644 index 92acd686a06..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/ap/prj.conf +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PRINTK=y -CONFIG_ARC_INIT=y -CONFIG_IPM=y -CONFIG_IPM_QUARK_SE=y -CONFIG_IPM_QUARK_SE_MASTER=y -CONFIG_IPM_CONSOLE_RECEIVER=y -CONFIG_TIMESLICE_SIZE=1 -CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/subsys/ipc/ipm_mailbox/ap/sample.yaml b/samples/subsys/ipc/ipm_mailbox/ap/sample.yaml deleted file mode 100644 index 7fd846d54d2..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/ap/sample.yaml +++ /dev/null @@ -1,7 +0,0 @@ -sample: - description: IPM Mailbox - name: IPM Mailbox -tests: - sample.subsys.ipc.ipm_mailbox.ap: - tags: ipm - platform_whitelist: quark_se_c1000_devboard diff --git a/samples/subsys/ipc/ipm_mailbox/ap/src/hello.c b/samples/subsys/ipc/ipm_mailbox/ap/src/hello.c deleted file mode 100644 index 1a24bec926b..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/ap/src/hello.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2012-2014 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -QUARK_SE_IPM_DEFINE(ping_ipm, 0, QUARK_SE_IPM_OUTBOUND); -QUARK_SE_IPM_DEFINE(message_ipm0, 1, QUARK_SE_IPM_OUTBOUND); -QUARK_SE_IPM_DEFINE(message_ipm1, 2, QUARK_SE_IPM_OUTBOUND); -QUARK_SE_IPM_DEFINE(message_ipm2, 3, QUARK_SE_IPM_OUTBOUND); - -/* specify delay between greetings (in ms); compute equivalent in ticks */ - -#define SLEEPTIME 1000 - -#define PING_TIME 1000 -#define STACKSIZE 2000 - -#define MSG_FIBER_PRI 6 -#define MAIN_FIBER_PRI 2 -#define PING_FIBER_PRI 4 -#define TASK_PRIO 7 - -K_THREAD_STACK_ARRAY_DEFINE(thread_stacks, 2, STACKSIZE); -static struct k_thread threads[2]; - -u32_t scss_reg(u32_t offset) -{ - volatile u32_t *ret = (volatile u32_t *)(SCSS_REGISTER_BASE + - offset); - - return *ret; -} - -static const char dat1[] = "abcdefghijklmno"; -static const char dat2[] = "pqrstuvwxyz0123"; - - -void message_source(struct device *ipm) -{ - u8_t counter = 0U; - - printk("sending messages for IPM device %p\n", ipm); - - while (1) { - ipm_send(ipm, 1, counter++, dat1, 16); - ipm_send(ipm, 1, counter++, dat2, 16); - } -} - - -void message_source_task_0(void) -{ - message_source(device_get_binding("message_ipm0")); -} - -void message_source_task_1(void) -{ - message_source(device_get_binding("message_ipm1")); -} - -void message_source_task_2(void) -{ - message_source(device_get_binding("message_ipm2")); -} - -void ping_source_thread(void *arg1, void *arg2, void *arg3) -{ - ARG_UNUSED(arg1); - ARG_UNUSED(arg2); - ARG_UNUSED(arg3); - - struct device *ipm = device_get_binding("ping_ipm"); - - while (1) { - k_sleep(PING_TIME); - printk("pinging sensor subsystem (ARC) for counter status\n"); - ipm_send(ipm, 1, 0, NULL, 0); - } -} - -void main_thread(void *arg1, void *arg2, void *arg3) -{ - ARG_UNUSED(arg1); - ARG_UNUSED(arg2); - ARG_UNUSED(arg3); - int ctr = 0; - u32_t ss_sts; - - while (1) { - /* say "hello" */ - printk("Hello from application processor (x86)! (%d) ", ctr++); - - ss_sts = scss_reg(SCSS_SS_STS); - switch (ss_sts) { - case 0x4000: - printk("Sensor Subsystem (ARC) is halted"); - break; - case 0x0400: - printk("Sensor Subsystem (ARC) is sleeping"); - break; - case 0: - printk("Sensor Subsystem (ARC) is running"); - break; - default: - printk("Sensor Subsystem (ARC) status: %x", ss_sts); - break; - } - - printk(", mailbox status: %x mask %x\n", scss_reg(0xac0), - scss_reg(0x4a0)); - - /* wait a while, then let other task have a turn */ - k_sleep(SLEEPTIME); - } -} - -K_THREAD_DEFINE(MSG_TASK0, STACKSIZE, message_source_task_0, NULL, NULL, NULL, - TASK_PRIO, 0, K_NO_WAIT); - -K_THREAD_DEFINE(MSG_TASK1, STACKSIZE, message_source_task_1, NULL, NULL, NULL, - TASK_PRIO, 0, K_NO_WAIT); - -K_THREAD_DEFINE(MSG_TASK2, STACKSIZE, message_source_task_2, NULL, NULL, NULL, - TASK_PRIO, 0, K_NO_WAIT); - -void main(void) -{ - printk("===== app started ========\n"); - - k_thread_create(&threads[0], &thread_stacks[0][0], STACKSIZE, - main_thread, 0, 0, 0, - K_PRIO_COOP(MAIN_FIBER_PRI), 0, 0); - - k_thread_create(&threads[1], &thread_stacks[1][0], STACKSIZE, - ping_source_thread, 0, 0, 0, - K_PRIO_COOP(PING_FIBER_PRI), 0, 0); -} - diff --git a/samples/subsys/ipc/ipm_mailbox/sensor/CMakeLists.txt b/samples/subsys/ipc/ipm_mailbox/sensor/CMakeLists.txt deleted file mode 100644 index bdf270a29c2..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/sensor/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(ipm_mailbox_sensor) - -target_include_directories(app PRIVATE $ENV{ZEPHYR_BASE}/drivers) -target_sources(app PRIVATE src/hello.c) diff --git a/samples/subsys/ipc/ipm_mailbox/sensor/prj.conf b/samples/subsys/ipc/ipm_mailbox/sensor/prj.conf deleted file mode 100644 index 34a219cffef..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/sensor/prj.conf +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_STDOUT_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_IPM=y -CONFIG_IPM_QUARK_SE=y -CONFIG_IPM_CONSOLE_SENDER=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=n diff --git a/samples/subsys/ipc/ipm_mailbox/sensor/sample.yaml b/samples/subsys/ipc/ipm_mailbox/sensor/sample.yaml deleted file mode 100644 index d6aaeeb6bc3..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/sensor/sample.yaml +++ /dev/null @@ -1,7 +0,0 @@ -sample: - description: IPM Mailbox - name: IPM Mailbox -tests: - sample.subsys.ipc.ipm_mailbox.sensor: - tags: ipm - platform_whitelist: quark_se_c1000_ss_devboard diff --git a/samples/subsys/ipc/ipm_mailbox/sensor/src/hello.c b/samples/subsys/ipc/ipm_mailbox/sensor/src/hello.c deleted file mode 100644 index d841e19bf04..00000000000 --- a/samples/subsys/ipc/ipm_mailbox/sensor/src/hello.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2012-2014 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include - -#include -#include -#include -#include -#include -#include - -QUARK_SE_IPM_DEFINE(ping_ipm, 0, QUARK_SE_IPM_INBOUND); -QUARK_SE_IPM_DEFINE(message_ipm0, 1, QUARK_SE_IPM_INBOUND); -QUARK_SE_IPM_DEFINE(message_ipm1, 2, QUARK_SE_IPM_INBOUND); -QUARK_SE_IPM_DEFINE(message_ipm2, 3, QUARK_SE_IPM_INBOUND); - -/* specify delay between greetings (in ms); compute equivalent in ticks */ - -#define SLEEPTIME 1100 - -#define STACKSIZE 2000 - -u8_t counters[3]; - -void ping_ipm_callback(void *context, u32_t id, volatile void *data) -{ - printk("counters: %d %d %d\n", counters[0], counters[1], counters[2]); -} - -static const char dat1[] = "abcdefghijklmno"; -static const char dat2[] = "pqrstuvwxyz0123"; - - -void message_ipm_callback(void *context, u32_t id, volatile void *data) -{ - u8_t *counter = (u8_t *)context; - char *datac = (char *)data; - const char *expected; - - if (*counter != id) { - printk("expected %d got %d\n", *counter, id); - } - - if (id & 0x1) { - expected = dat2; - } else { - expected = dat1; - } - - if (strcmp(expected, datac)) { - printk("unexpected data payload\n"); - } - (*counter)++; -} - -void main(void) -{ - struct device *ipm; - - ipm = device_get_binding("ping_ipm"); - ipm_register_callback(ipm, ping_ipm_callback, NULL); - ipm_set_enabled(ipm, 1); - - ipm = device_get_binding("message_ipm0"); - ipm_register_callback(ipm, message_ipm_callback, &counters[0]); - ipm_set_enabled(ipm, 1); - - ipm = device_get_binding("message_ipm1"); - ipm_register_callback(ipm, message_ipm_callback, &counters[1]); - ipm_set_enabled(ipm, 1); - - ipm = device_get_binding("message_ipm2"); - ipm_register_callback(ipm, message_ipm_callback, &counters[2]); - ipm_set_enabled(ipm, 1); - - - while (1) { - /* say "hello" */ - printk("Hello from ARC!\n"); - - k_sleep(SLEEPTIME); - } -} diff --git a/samples/subsys/usb/hid/README.rst b/samples/subsys/usb/hid/README.rst index b6eef85fee8..49c2b4a3365 100644 --- a/samples/subsys/usb/hid/README.rst +++ b/samples/subsys/usb/hid/README.rst @@ -20,11 +20,11 @@ Building and Running ******************** This sample can be built for multiple boards, in this example we will build it -for the quark_se_c1000_devboard board: +for the reel_board board: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/hid - :board: quark_se_c1000_devboard + :board: reel_board :goals: build :compact: diff --git a/samples/subsys/usb/mass/README.rst b/samples/subsys/usb/mass/README.rst index b9d5a5cdb7a..39ace5f4bfd 100644 --- a/samples/subsys/usb/mass/README.rst +++ b/samples/subsys/usb/mass/README.rst @@ -23,11 +23,11 @@ Building and Running This sample can be built for multiple boards. The selection between a RAM-based or a FLASH-based disk can be selected using the ``overlay-ram-disk.conf`` or the ``overlay-flash-disk.conf`` overlays. In this example we will build the sample -with a RAM-based disk and for the quark_se_c1000_devboard board: +with a RAM-based disk: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: quark_se_c1000_devboard + :board: reel_board :gen-args: -DOVERLAY_CONFIG="overlay-ram-disk.conf" :goals: build :compact: diff --git a/scripts/sanity_chk/sanity_compare.args b/scripts/sanity_chk/sanity_compare.args index ae0bbd1e882..76d73582715 100644 --- a/scripts/sanity_chk/sanity_compare.args +++ b/scripts/sanity_chk/sanity_compare.args @@ -8,11 +8,3 @@ frdm_k64f nrf51_pca10028 -p nrf52_pca10040 --p -quark_d2000_crb --p -quark_se_c1000_devboard --p -quark_se_c1000_ss_devboard --p -altera_max10 diff --git a/scripts/sanitycheck b/scripts/sanitycheck index 3fac9451486..a7d3cf7a64a 100755 --- a/scripts/sanitycheck +++ b/scripts/sanitycheck @@ -141,9 +141,9 @@ pairs: The ':' operator compiles the string argument as a regular expression, and then returns a true value only if the symbol's value in the environment - matches. For example, if CONFIG_SOC="quark_se" then + matches. For example, if CONFIG_SOC="stm32f107xc" then - filter = CONFIG_SOC : "quark.*" + filter = CONFIG_SOC : "stm.*" Would match it. diff --git a/soc/arc/quark_se_c1000_ss/CMakeLists.txt b/soc/arc/quark_se_c1000_ss/CMakeLists.txt deleted file mode 100644 index afe37d5f828..00000000000 --- a/soc/arc/quark_se_c1000_ss/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_include_directories(${ZEPHYR_BASE}/soc/x86/intel_quark) - -zephyr_cc_option(-mcpu=quarkse_em -mno-sdata) - -zephyr_compile_definitions_ifdef( - CONFIG_SOC_QUARK_SE_C1000_SS - QM_SENSOR=1 - SOC_SERIES=quark_se - ) - -zephyr_sources( - soc.c - soc_config.c - ) - -zephyr_sources_ifdef(CONFIG_SYS_POWER_MANAGEMENT - power.c - soc_power.S - ) diff --git a/soc/arc/quark_se_c1000_ss/Kconfig b/soc/arc/quark_se_c1000_ss/Kconfig deleted file mode 100644 index 6aa40fadef2..00000000000 --- a/soc/arc/quark_se_c1000_ss/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if ARC && SOC_QUARK_SE_C1000_SS - -if IPM -config QUARK_SE_SS_IPM_IRQ_PRI - int "IPM interrupt priority" - default 1 - help - Priority level for interrupts coming in from the inter-processor - mailboxes. - -endif # IPM -endif # SOC_QUARK_SE_C1000_SS diff --git a/soc/arc/quark_se_c1000_ss/Kconfig.defconfig b/soc/arc/quark_se_c1000_ss/Kconfig.defconfig deleted file mode 100644 index 9ae0dddb89c..00000000000 --- a/soc/arc/quark_se_c1000_ss/Kconfig.defconfig +++ /dev/null @@ -1,232 +0,0 @@ -# -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2015-2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_QUARK_SE_C1000_SS - -config SOC - default "quark_se_c1000_ss" - -config NUM_IRQ_PRIO_LEVELS - # This processor supports only 2 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 68 - -config RGF_NUM_BANKS - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32000000 - -config HARVARD - default n - -config QMSI - def_bool y - -if COUNTER - -config RTC_QMSI - default y - -endif # RTC - -if PWM -config PWM_QMSI - default y -endif # PWM - -if PINMUX -config PINMUX_QMSI - default y -endif - -if GPIO - -config GPIO_QMSI - default n - -if GPIO_QMSI - -config GPIO_QMSI_0 - default y - -config GPIO_QMSI_1 - default y - -endif # GPIO_QMSI - -config GPIO_QMSI_SS - default y - -if GPIO_QMSI_SS - -config GPIO_QMSI_SS_0 - default y - -config GPIO_QMSI_SS_1 - default y - -endif # GPIO_QMSI_SS - -endif # GPIO - - -if I2C - -config I2C_QMSI - default n - -if I2C_QMSI -config I2C_0 - default y - -config I2C_1 - default y - -config I2C_SDA_SETUP - default 2 - -config I2C_SDA_TX_HOLD - default 16 - -config I2C_SDA_RX_HOLD - default 24 - -endif - -config I2C_QMSI_SS - default y - -if I2C_QMSI_SS -config I2C_SS_0 - default y - -config I2C_SS_1 - default y - -config I2C_SS_SDA_SETUP - default 2 - -config I2C_SS_SDA_HOLD - default 10 - -endif - -endif # I2C - -if ADC -config ADC_INTEL_QUARK_SE_C1000_SS - default y -endif - -if BT_H4 - -config UART_QMSI_0 - default y - -config UART_QMSI_0_HW_FC - default y - -endif # BT_H4 - -if UART_QMSI - -config UART_QMSI_1 - default y - -endif # UART_QMSI - -if SPI - -config SPI_DW - default y - -if SPI_DW - -config SPI_DW_FIFO_DEPTH - default 7 - -config CLOCK_CONTROL - default y - -config CLOCK_CONTROL_QUARK_SE - default y - -config CLOCK_CONTROL_QUARK_SE_SENSOR - default y - -config SPI_0 - default y - -config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE - default n - -config SPI_DW_PORT_0_CLOCK_GATE - default y - -config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME - default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME - -config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS - default 3 - -config SPI_1 - default y - -config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE - default n - -config SPI_DW_PORT_1_CLOCK_GATE - default y - -config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME - default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME - -config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS - default 4 - -endif # SPI_DW -endif # SPI - -if AIO_COMPARATOR - -config AIO_COMPARATOR_QMSI - default y - -endif # AIO_COMPARATOR - -if WATCHDOG - -config WDT_QMSI - default y -endif # WATCHDOG - -if DMA - -config DMA_QMSI - default y - -endif # DMA - -if COUNTER - -config AON_COUNTER_QMSI - default y - -config AON_TIMER_QMSI - default y - -config AON_TIMER_IRQ_PRI - default 0 - -endif # COUNTER - -endif #SOC_QUARK_SE_C1000_SS diff --git a/soc/arc/quark_se_c1000_ss/Kconfig.soc b/soc/arc/quark_se_c1000_ss/Kconfig.soc deleted file mode 100644 index 2d1ebd4073c..00000000000 --- a/soc/arc/quark_se_c1000_ss/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QUARK_SE_C1000_SS - bool "Intel Quark SE C1000- Sensor Sub System" - select HAS_SYS_POWER_STATE_SLEEP_1 - select HAS_SYS_POWER_STATE_SLEEP_2 - select HAS_SYS_POWER_STATE_DEEP_SLEEP_1 - select HAS_SYS_POWER_STATE_DEEP_SLEEP_2 - select HAS_SYS_POWER_STATE_DEEP_SLEEP_3 - select HAS_QMSI - select HAS_SPI_DW diff --git a/soc/arc/quark_se_c1000_ss/dts_fixup.h b/soc/arc/quark_se_c1000_ss/dts_fixup.h deleted file mode 100644 index 3577a02220a..00000000000 --- a/soc/arc/quark_se_c1000_ss/dts_fixup.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/* SoC level DTS fixup file */ - -#define DT_UART_QMSI_0_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002000_CLOCKS_CLOCK_FREQUENCY -#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED -#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL -#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 -#define DT_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY - -#define DT_UART_QMSI_1_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002400_CLOCKS_CLOCK_FREQUENCY -#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED -#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL -#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 -#define DT_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY - -#define SRAM_START CONFIG_SRAM_BASE_ADDRESS -#define SRAM_SIZE CONFIG_SRAM_SIZE - -#define FLASH_START CONFIG_FLASH_BASE_ADDRESS -#define FLASH_SIZE CONFIG_FLASH_SIZE - -#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS -#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) - -#define DT_I2C_SS_0_NAME DT_INTEL_QMSI_SS_I2C_80012000_LABEL -#define DT_I2C_SS_0_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR -#define DT_I2C_SS_0_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY -#define DT_I2C_SS_0_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX -#define DT_I2C_SS_0_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY -#define DT_I2C_SS_0_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX -#define DT_I2C_SS_0_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY -#define DT_I2C_SS_0_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP -#define DT_I2C_SS_0_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY -#define DT_I2C_SS_0_BITRATE DT_INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY -#define DT_I2C_SS_1_NAME DT_INTEL_QMSI_SS_I2C_80012100_LABEL -#define DT_I2C_SS_1_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR -#define DT_I2C_SS_1_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY -#define DT_I2C_SS_1_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX -#define DT_I2C_SS_1_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY -#define DT_I2C_SS_1_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX -#define DT_I2C_SS_1_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY -#define DT_I2C_SS_1_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP -#define DT_I2C_SS_1_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY -#define DT_I2C_SS_1_BITRATE DT_INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY - -#define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL -#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY -#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 -#define DT_I2C_0_IRQ_PRI DT_INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY -#define CONFIG_I2C_1_NAME DT_INTEL_QMSI_I2C_B0002C00_LABEL -#define DT_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY -#define DT_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 -#define DT_I2C_1_IRQ_PRI DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY - -#define DT_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL -#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 -#define DT_RTC_0_IRQ_PRI DT_INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY - -#define DT_GPIO_QMSI_SS_0_NAME DT_INTEL_QMSI_SS_GPIO_80017800_LABEL -#define DT_GPIO_QMSI_SS_0_IRQ DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0 -#define DT_GPIO_QMSI_SS_0_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY - -#define DT_GPIO_QMSI_SS_1_NAME DT_INTEL_QMSI_SS_GPIO_80017900_LABEL -#define DT_GPIO_QMSI_SS_1_IRQ DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0 -#define DT_GPIO_QMSI_SS_1_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY - -#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL -#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 -#define DT_GPIO_QMSI_0_IRQ_PRI DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY -#define DT_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL -#define DT_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 -#define DT_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY - -#define DT_ADC_0_IRQ DT_SNPS_DW_ADC_80015000_IRQ_NORMAL -#define DT_ADC_IRQ_ERR DT_SNPS_DW_ADC_80015000_IRQ_ERROR -#define DT_ADC_0_IRQ_PRI DT_SNPS_DW_ADC_80015000_IRQ_0_PRIORITY -#define DT_ADC_0_NAME DT_SNPS_DW_ADC_80015000_LABEL -#define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS - -#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS -#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010000_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL -#define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT -#define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY -#define DT_SPI_0_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL -#define DT_SPI_0_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL_PRIORITY -#define DT_SPI_0_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ -#define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY - -#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS -#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010100_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL -#define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT -#define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY -#define DT_SPI_1_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL -#define DT_SPI_1_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL_PRIORITY -#define DT_SPI_1_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ -#define DT_SPI_1_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY - -#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL -#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 -#define DT_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY -#define DT_WDT_0_IRQ_FLAGS 0 -/* End of SoC Level DTS fixup file */ diff --git a/soc/arc/quark_se_c1000_ss/linker.ld b/soc/arc/quark_se_c1000_ss/linker.ld deleted file mode 100644 index ef5392ba1f0..00000000000 --- a/soc/arc/quark_se_c1000_ss/linker.ld +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2014-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/** - * @brief Linker script for the Quark SE platform, both standard images and XIP - * images. - */ - -/* Flash base address and size */ -#define FLASH_START CONFIG_FLASH_BASE_ADDRESS /* Flash bank 1 */ -#define FLASH_SIZE CONFIG_FLASH_SIZE - -/* - * SRAM base address and size - * - * Internal SRAM includes the exception vector table at reset, which is at - * the beginning of the region. - */ -#define SRAM_START CONFIG_SRAM_BASE_ADDRESS -#define SRAM_SIZE CONFIG_SRAM_SIZE - -/* Data Closely Coupled Memory (DCCM) base address and size */ -#define DCCM_START DT_DCCM_BASE_ADDRESS -#define DCCM_SIZE DT_DCCM_SIZE - -#include diff --git a/soc/arc/quark_se_c1000_ss/power.c b/soc/arc/quark_se_c1000_ss/power.c deleted file mode 100644 index 4b8109a597d..00000000000 --- a/soc/arc/quark_se_c1000_ss/power.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "power_states.h" -#include "ss_power_states.h" -#include "vreg.h" - -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) -extern void z_power_soc_sleep(void); -extern void z_power_soc_deep_sleep(void); -extern void z_power_soc_lpss_mode(void); - -static void deep_sleep(enum power_states state) -{ - qm_power_soc_set_ss_restore_flag(); - - switch (state) { - case SYS_POWER_STATE_DEEP_SLEEP_2: - z_power_soc_sleep(); - break; - case SYS_POWER_STATE_DEEP_SLEEP_3: - z_power_soc_deep_sleep(); - break; - default: - break; - } -} -#endif - -void sys_set_power_state(enum power_states state) -{ - switch (state) { -#if (defined(CONFIG_SYS_POWER_SLEEP_STATES)) - case SYS_POWER_STATE_SLEEP_1: - qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON); - break; - case SYS_POWER_STATE_SLEEP_2: - qm_ss_power_cpu_ss2(); - break; -#endif -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) - case SYS_POWER_STATE_DEEP_SLEEP_1: - qm_ss_power_soc_lpss_enable(); - qm_power_soc_set_ss_restore_flag(); - z_power_soc_lpss_mode(); - break; - case SYS_POWER_STATE_DEEP_SLEEP_2: - case SYS_POWER_STATE_DEEP_SLEEP_3: - deep_sleep(state); - break; -#endif - default: - break; - } -} - -void _sys_pm_power_state_exit_post_ops(enum power_states state) -{ - switch (state) { -#if (defined(CONFIG_SYS_POWER_SLEEP_STATES)) - case SYS_POWER_STATE_SLEEP_2: - { - /* Expire the timer as it is disabled in SS2. */ - u32_t limit = z_arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT); - z_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1); - } - case SYS_POWER_STATE_SLEEP_1: - __builtin_arc_seti(0); - break; -#endif -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) - case SYS_POWER_STATE_DEEP_SLEEP_1: - qm_ss_power_soc_lpss_disable(); - - /* If flag is cleared it means the system entered in - * sleep state while we were in LPS. In that case, we - * must set ARC_READY flag so x86 core can continue - * its execution. - */ - if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) { - z_quark_se_ss_ready(); - __builtin_arc_seti(0); - } else { - QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY; - QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP; - } - break; - case SYS_POWER_STATE_DEEP_SLEEP_2: - case SYS_POWER_STATE_DEEP_SLEEP_3: - /* Route RTC interrupt to the current core */ - QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask); - __builtin_arc_seti(0); - break; -#endif - default: - break; - } -} diff --git a/soc/arc/quark_se_c1000_ss/soc.c b/soc/arc/quark_se_c1000_ss/soc.c deleted file mode 100644 index 38c88fd3f54..00000000000 --- a/soc/arc/quark_se_c1000_ss/soc.c +++ /dev/null @@ -1,32 +0,0 @@ -/* system.c - system/hardware module for quark_se_ss BSP */ - -/* - * Copyright (c) 2014-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * This module provides routines to initialize and support board-level hardware - * for the Quark SE platform. - */ - -#include -#include "soc.h" -#include - -/** - * @brief perform basic hardware initialization - * - * RETURNS: N/A - */ -static int quark_se_arc_init(struct device *arg) -{ - ARG_UNUSED(arg); - - quark_se_ss_ready(); - - return 0; -} - -SYS_INIT(quark_se_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arc/quark_se_c1000_ss/soc.h b/soc/arc/quark_se_c1000_ss/soc.h deleted file mode 100644 index 547d0be349b..00000000000 --- a/soc/arc/quark_se_c1000_ss/soc.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2014-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Board configuration macros for Quark SE Sensor Subsystem - * - * This header file is used to specify and describe board-level - * aspects for the Quark SE Sensor Subsystem. - */ - -#ifndef _BOARD__H_ -#define _BOARD__H_ - -#include - -/* default system clock */ - -#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32) - -/* address bases */ - -#define SCSS_REGISTER_BASE 0xB0800000 /*Sensor Subsystem Base*/ - -#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */ - -#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */ -#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */ -#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */ - -#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */ -#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */ - -#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */ -#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */ - -/* IRQs */ - -/* The CPU-visible IRQ numbers change between the ARC and IA cores, - * and QMSI itself has no easy way to pick the correct one, though it - * does have the necessary information to do it ourselves (in the meantime). - * This macro will be used by the shim drivers to get the IRQ number to - * use, and it should always be called using the QM_IRQ_*_INT macro - * provided by QMSI. - */ -#define IRQ_GET_NUMBER(_irq) _irq##_VECTOR - -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 -#define IRQ_I2C0_RX_AVAIL 18 -#define IRQ_I2C0_TX_REQ 19 -#define IRQ_I2C0_STOP_DET 20 -#define IRQ_I2C0_ERR 21 -#define IRQ_I2C1_RX_AVAIL 22 -#define IRQ_I2C1_TX_REQ 23 -#define IRQ_I2C1_STOP_DET 24 -#define IRQ_I2C1_ERR 25 - -#define IRQ_ADC_ERR 18 -#define IRQ_ADC_IRQ 19 -#define IRQ_GPIO0_INTR 20 -#define IRQ_GPIO1_INTR 21 -#define IRQ_I2C_MST0_INTR 36 -#define IRQ_I2C_MST1_INTR 37 -#define IRQ_SPI_MST0_INTR 38 -#define IRQ_SPI_MST1_INTR 39 -#define IRQ_SPI_SLV_INTR 40 -#define IRQ_UART0_INTR 41 -#define IRQ_UART1_INTR 42 -#define IRQ_I2S_INTR 43 -#define IRQ_GPIO_INTR 44 -#define IRQ_PWM_TIMER_INTR 45 -#define IRQ_USB_INTR 46 -#define IRQ_RTC_INTR 47 -#define IRQ_WDOG_INTR 48 -#define IRQ_DMA_CHAN0 49 -#define IRQ_DMA_CHAN1 50 -#define IRQ_DMA_CHAN2 51 -#define IRQ_DMA_CHAN3 52 -#define IRQ_DMA_CHAN4 53 -#define IRQ_DMA_CHAN5 54 -#define IRQ_DMA_CHAN6 55 -#define IRQ_DMA_CHAN7 56 -#define IRQ_MAILBOXES_INTR 57 -#define IRQ_COMPARATORS_INTR 58 -#define IRQ_SYS_PMU_INTR 59 -#define IRQ_DMA_CHANS_ERR 60 -#define IRQ_INT_SRAM_CTLR 61 -#define IRQ_INT_FLASH0_CTLR 62 -#define IRQ_INT_FLASH1_CTLR 63 -#define IRQ_ALWAYS_ON_TMR 64 -#define IRQ_ADC_PWR 65 -#define IRQ_ADC_CALIB 66 -#define IRQ_ALWAYS_ON_GPIO 67 - -#ifndef _ASMLANGUAGE - -#include -#include -#include - -#define INT_ENABLE_ARC ~(0x00000001 << 8) -#define INT_ENABLE_ARC_BIT_POS (8) - -/* - * I2C - */ -#define I2C_SS_0_ERR_VECTOR 22 -#define I2C_SS_0_ERR_MASK 0x410 -#define I2C_SS_0_RX_VECTOR 23 -#define I2C_SS_0_RX_MASK 0x414 -#define I2C_SS_0_TX_VECTOR 24 -#define I2C_SS_0_TX_MASK 0x418 -#define I2C_SS_0_STOP_VECTOR 25 -#define I2C_SS_0_STOP_MASK 0x41C - -#define I2C_SS_1_ERR_VECTOR 26 -#define I2C_SS_1_ERR_MASK 0x420 -#define I2C_SS_1_RX_VECTOR 27 -#define I2C_SS_1_RX_MASK 0x424 -#define I2C_SS_1_TX_VECTOR 28 -#define I2C_SS_1_TX_MASK 0x428 -#define I2C_SS_1_STOP_VECTOR 29 -#define I2C_SS_1_STOP_MASK 0x42C - -#define DT_I2C_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) -#define DT_I2C_1_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) - - -/* - * GPIO - */ -#define GPIO_DW_IO_ACCESS - -#define DT_GPIO_DW_0_BASE_ADDR 0x80017800 -#define DT_GPIO_DW_0_IRQ 20 -#define DT_GPIO_DW_0_BITS 8 -#define GPIO_DW_PORT_0_INT_MASK (SCSS_REGISTER_BASE + 0x408) - -#define DT_GPIO_DW_1_BASE_ADDR 0x80017900 -#define DT_GPIO_DW_1_IRQ 21 -#define DT_GPIO_DW_1_BITS 8 -#define GPIO_DW_PORT_1_INT_MASK (SCSS_REGISTER_BASE + 0x40C) - -#if defined(CONFIG_IOAPIC) -#define DT_GPIO_DW_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) -#define GPIO_DW_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) -#else -#define DT_GPIO_DW_0_IRQ_FLAGS 0 -#define GPIO_DW_1_IRQ_FLAGS 0 -#endif - -#define DT_GPIO_QMSI_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) -#define DT_GPIO_QMSI_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) - -/* - * UART - */ -#define DT_UART_QMSI_0_IRQ_FLAGS 0 -#define DT_UART_QMSI_1_IRQ_FLAGS 0 - -/* - * SPI - */ - -#ifdef CONFIG_SPI_DW - -#define SPI_DW_PORT_0_ERROR_INT_MASK (SCSS_REGISTER_BASE + 0x430) -#define SPI_DW_PORT_0_RX_INT_MASK (SCSS_REGISTER_BASE + 0x434) -#define SPI_DW_PORT_0_TX_INT_MASK (SCSS_REGISTER_BASE + 0x438) - -#define SPI_DW_PORT_1_ERROR_INT_MASK (SCSS_REGISTER_BASE + 0x43C) -#define SPI_DW_PORT_1_RX_INT_MASK (SCSS_REGISTER_BASE + 0x440) -#define SPI_DW_PORT_1_TX_INT_MASK (SCSS_REGISTER_BASE + 0x444) - -#define DT_SPI_DW_IRQ_FLAGS 0 - -#define SPI_DW_PORT_2_REGS 0xB0001000 -#define SPI_DW_PORT_2_IRQ IRQ_SPI_MST0_INTR -#define SPI_DW_PORT_2_INT_MASK (SCSS_REGISTER_BASE + 0x454) - -#define SPI_DW_PORT_3_REGS 0xB0001400 -#define SPI_DW_PORT_3_IRQ IRQ_SPI_MST1_INTR -#define SPI_DW_PORT_3_INT_MASK (SCSS_REGISTER_BASE + 0x458) - -#endif /* CONFIG_SPI_DW */ - -/* Clock */ -#define CLOCK_PERIPHERAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x18) -#define CLOCK_EXTERNAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x24) -#define CLOCK_SENSOR_BASE_ADDR (SCSS_REGISTER_BASE + 0x28) -#define CLOCK_SYSTEM_CLOCK_CONTROL (SCSS_REGISTER_BASE + \ - SCSS_CCU_SYS_CLK_CTL) - -/* - * RTC - */ - -#define DT_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) - - -static inline void quark_se_ss_ready(void) -{ - shared_data->flags |= ARC_READY; -} - -#endif /* !_ASMLANGUAGE */ - -#endif /* _BOARD__H_ */ diff --git a/soc/arc/quark_se_c1000_ss/soc_config.c b/soc/arc/quark_se_c1000_ss/soc_config.c deleted file mode 100644 index 2954be23bdb..00000000000 --- a/soc/arc/quark_se_c1000_ss/soc_config.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "soc.h" - -#if CONFIG_IPM_QUARK_SE -#include -#include - -static int arc_quark_se_ipm_init(void) -{ - IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_SS_IPM_IRQ_PRI, - quark_se_ipm_isr, NULL, 0); - irq_enable(QUARK_SE_IPM_INTERRUPT); - return 0; -} - -static struct quark_se_ipm_controller_config_info ipm_controller_config = { - .controller_init = arc_quark_se_ipm_init -}; -DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize, - NULL, &ipm_controller_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &ipm_quark_se_api_funcs); - -#if CONFIG_IPM_CONSOLE_SENDER -#include -QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_OUTBOUND); - -static struct ipm_console_sender_config_info quark_se_ipm_sender_config = { - .bind_to = "quark_se_ipm4", - .flags = IPM_CONSOLE_PRINTK | IPM_CONSOLE_STDOUT, -}; -DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init, - NULL, &quark_se_ipm_sender_config, - POST_KERNEL, CONFIG_IPM_CONSOLE_INIT_PRIORITY); - -#endif /* CONFIG_IPM_CONSOLE_SENDER */ -#endif /* CONFIG_IPM_QUARK_SE */ diff --git a/soc/arc/quark_se_c1000_ss/soc_power.S b/soc/arc/quark_se_c1000_ss/soc_power.S deleted file mode 100644 index 4be678763f4..00000000000 --- a/soc/arc/quark_se_c1000_ss/soc_power.S +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES -GDATA(_pm_arc_context) - -GTEXT(sys_resume_from_deep_sleep) -GTEXT(z_power_restore_cpu_context) -GTEXT(z_power_soc_sleep) -GTEXT(z_power_soc_deep_sleep) -GTEXT(z_power_soc_lpss_mode) - -#define GPS0_REGISTER 0xb0800100 -#define GP0_REGISTER 0xb0800114 -#define GP0_BIT_SLEEP_READY 0 -#define RESTORE_SS_BIT 2 -#define SLEEP_INTR_ENABLED_BIT 4 -#define SLEEP_MODE_RTC_ENABLED_BIT 5 - -SECTION_FUNC(TEXT, _sys_resume_from_deep_sleep) - /* Check is this wakeup after sleep event. */ - ld r0,[GPS0_REGISTER] - bbit1 r0,RESTORE_SS_BIT,restore - j_s [blink] /* Jump to context of BLINK register. */ - -restore: - bclr_s r0,r0,RESTORE_SS_BIT - st r0,[GPS0_REGISTER] - - /* Enable I-Cache */ - sr 1, [_ARC_V2_IC_CTRL] - - j @sys_restore_cpu_context - -SECTION_FUNC(TEXT, save_cpu_context) - mov_s r1, _kernel - ld_s r2, [r1, _kernel_offset_to_current] - - _save_callee_saved_regs - - j_s [blink] /* Jump to context of BLINK register. */ - -SECTION_FUNC(TEXT, z_power_soc_sleep) - /* - * Save the return address. - * The restore function will pop this and jump - * back to the caller. - */ - push_s blink - - /* Do not link to preserve blink */ - jl @save_cpu_context - j @qm_power_soc_sleep - /* Does not return */ - -SECTION_FUNC(TEXT, z_power_soc_deep_sleep) - /* - * Save the return address. - * The restore function will pop this and jump - * back to the caller. - */ - push_s blink - - /* Do not link to preserve blink */ - jl @save_cpu_context - j @qm_power_soc_deep_sleep - /* Does not return */ - -SECTION_FUNC(TEXT, z_power_soc_lpss_mode) - /* - * Setup 'sleep' instruction operand. - */ - - /* Get interrupt priority from status32 registers. */ - lr r0, [_ARC_V2_STATUS32] - lsr r0, r0 - and r0, r0, 0xF - - /* Enable interrupts */ - bset r0, r0, SLEEP_INTR_ENABLED_BIT - - /* Set 'sleep' mode corresponding to SS2 state i.e. core disabled, - * timers disabled, RTC enabled. - */ - bset r0, r0, SLEEP_MODE_RTC_ENABLED_BIT - - /* - * Save the return address. - * The restore function will pop this and jump - * back to the caller. - */ - push_s blink - - jl @save_cpu_context - - ld r1, [GP0_REGISTER] - bset r1, r1, GP0_BIT_SLEEP_READY - st r1, [GP0_REGISTER] - sleep r0 - - /* If we reach this code it means the x86 core didn't put the - * system in SYS_POWER_STATE_DEEP_SLEEP_3 state while we were - * in LPS. Then discard saved context. - */ - _discard_callee_saved_regs - - pop_s blink - j_s [blink] - -SECTION_FUNC(TEXT, sys_restore_cpu_context) - mov_s r1, _kernel - ld_s r2, [r1, _kernel_offset_to_current] - - _load_callee_saved_regs - - /* Restore return address */ - pop_s blink - - j_s [blink] /* Jump to context of BLINK register. */ -#endif diff --git a/soc/arc/quark_se_c1000_ss/soc_power.h b/soc/arc/quark_se_c1000_ss/soc_power.h deleted file mode 100644 index 4a77fd599c8..00000000000 --- a/soc/arc/quark_se_c1000_ss/soc_power.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC_POWER_H_ -#define _SOC_POWER_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Bit 0 from GP0 register is used internally by the kernel - * to handle PM multicore support. Any change on QMSI and/or - * bootloader which affects this bit should take it in - * consideration. - */ -#define GP0_BIT_SLEEP_READY BIT(0) - -/* - * Power state map: - * SYS_POWER_STATE_SLEEP_1: SS1 state with Timer ON - * SYS_POWER_STATE_SLEEP_2: SS1 state with Timer ON - * SYS_POWER_STATE_DEEP_SLEEP_1: SS2 with LPSS enabled state - * SYS_POWER_STATE_DEEP_SLEEP_2: SLEEP state - * SYS_POWER_STATE_DEEP_SLEEP_3: SLEEP state with LPMODE enabled - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_POWER_H_ */ diff --git a/soc/x86/intel_quark/Kconfig b/soc/x86/intel_quark/Kconfig deleted file mode 100644 index 1a065e05735..00000000000 --- a/soc/x86/intel_quark/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_QUARK - bool - -if SOC_FAMILY_QUARK -config SOC_FAMILY - string - default "intel_quark" -endif - -source "soc/x86/intel_quark/*/Kconfig.soc" - -source "soc/x86/intel_quark/*/Kconfig" diff --git a/soc/x86/intel_quark/Kconfig.defconfig b/soc/x86/intel_quark/Kconfig.defconfig deleted file mode 100644 index ba904cb7b61..00000000000 --- a/soc/x86/intel_quark/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/x86/intel_quark/*/Kconfig.defconfig.series" diff --git a/soc/x86/intel_quark/Kconfig.soc b/soc/x86/intel_quark/Kconfig.soc deleted file mode 100644 index 3ab62aa9104..00000000000 --- a/soc/x86/intel_quark/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/x86/intel_quark/*/Kconfig.series" diff --git a/soc/x86/intel_quark/include/pinmux_quark_mcu.h b/soc/x86/intel_quark/include/pinmux_quark_mcu.h deleted file mode 100644 index ee897012300..00000000000 --- a/soc/x86/intel_quark/include/pinmux_quark_mcu.h +++ /dev/null @@ -1,63 +0,0 @@ -/* pinmux_quark_mcu.h - pinmux operation for generic Quark MCU boards */ - -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define PINMUX_PULLUP_OFFSET 0x00 -#define PINMUX_SLEW_OFFSET 0x10 -#define PINMUX_INPUT_OFFSET 0x20 -#define PINMUX_SELECT_OFFSET 0x30 - -#define PINMUX_SELECT_REGISTER(base, reg_offset) \ - (base + PINMUX_SELECT_OFFSET + (reg_offset << 2)) - -/* - * A little decyphering of what is going on here: - * - * Each pinmux register rperesents a bank of 16 pins, 2 bits per pin for a total - * of four possible settings per pin. - * - * The first argument to the macro is name of the u32_t's that is being used - * to contain the bit patterns for all the configuration registers. The pin - * number divided by 16 selects the correct register bank based on the pin - * number. - * - * The pin number % 16 * 2 selects the position within the register bank for the - * bits controlling the pin. - * - * All but the lower two bits of the config values are masked off to ensure - * that we don't inadvertently affect other pins in the register bank. - */ -#define PIN_CONFIG(A, _pin, _func) \ - (A[((_pin) / 16)] |= ((0x3 & (_func)) << (((_pin) % 16) * 2))) - -static inline int z_quark_mcu_set_mux(u32_t base, u32_t pin, u8_t func) -{ - /* - * the registers are 32-bit wide, but each pin requires 1 bit - * to set the input enable bit. - */ - u32_t register_offset = (pin / 32) * 4U; - /* - * Now figure out what is the full address for the register - * we are looking for. Add the base register to the register_mask - */ - volatile u32_t *mux_register = (u32_t *)(base + register_offset); - - /* - * Finally grab the pin offset within the register - */ - u32_t pin_offset = pin % 32; - - /* - * MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a - * 32-bit register. - */ - (*(mux_register)) = ((*(mux_register)) & ~(0x1 << pin_offset)) | - ((func & 0x01) << pin_offset); - - return 0; -} diff --git a/soc/x86/intel_quark/quark_se/CMakeLists.txt b/soc/x86/intel_quark/quark_se/CMakeLists.txt deleted file mode 100644 index f43fa57541d..00000000000 --- a/soc/x86/intel_quark/quark_se/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_compile_definitions_ifdef( - CONFIG_SOC_QUARK_SE_C1000 - QM_LAKEMONT - SOC_SERIES=quark_se - ) - -zephyr_cc_option(-march=lakemont -mtune=lakemont -msoft-float) - -zephyr_sources( - soc.c - soc_config.c - eoi.c - ) - -zephyr_sources_ifdef(CONFIG_SYS_POWER_MANAGEMENT - power.c - soc_power.S - ) diff --git a/soc/x86/intel_quark/quark_se/Kconfig b/soc/x86/intel_quark/quark_se/Kconfig deleted file mode 100644 index 9ac5a67102f..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig +++ /dev/null @@ -1,84 +0,0 @@ -# Kconfig - Quark SE configuration options - -# -# Copyright (c) 2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if X86 && SOC_QUARK_SE_C1000 - -config EOI_FORWARDING_BUG - bool - default y - help - Quark SE LOAPIC has issues with forwarding EOI to the IOAPIC for level - triggered interrupts, this is a SW workaround. - -config SS_RESET_VECTOR - hex "Sensor Subsystem Reset Vector" - default 0x40000000 - help - Sensor subsystem reset vector. This value is needed to init the ARC - system on the SoC. - -config ARC_INIT - bool "Quark SE ARC Kickoff" - help - Allows x86 processor to kickoff the ARC slave processor. - -config ARC_GDB_ENABLE - bool "Allows the usage of GDB with the ARC processor." - depends on ARC_INIT - help - This option will stop the master processor from boot-strapping - the ARC slave processor. This will allow GDB to halt and - engage the ARC processor to proceed step by step execution. - -if IPM -config QUARK_SE_IPM_IRQ_PRI - int "IPM interrupt priority" - default 2 - help - Priority level for interrupts coming in from the inter-processor - mailboxes. - -if IPM_CONSOLE_RECEIVER -config QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 - int "IPM Console Ring Buffer Size" - default 256 - help - Size of the buffer for the console receiver, for incoming - console messages from the ARC side. Must be a power of 2. -endif -endif - -config BSP_SHARED_RESTORE_INFO_RAM_ADDR - hex "Address of the restore information in RAM shared with the QMSI Bootloader" - default 0xA8013FDC - help - Address of the memory shared between the BSP and the Bootloader in order - to store restore information. - -config BSP_SHARED_RESTORE_INFO_SIZE - hex "Size of the restore information in RAM shared with the QMSI Bootloader" - default 0x4 - help - Size of the memory shared between the BSP and the Bootloader in order - to store restore information. - -config SHARED_GDT_RAM_ADDR - hex "Address of the GDT in RAM shared with the QMSI Bootloader" - default 0xA8013FE0 - help - Address of the memory shared between the BSP and the Bootloader in order - to store the GDT. - -config SHARED_GDT_RAM_SIZE - hex "Size of the GDT in RAM shared with the QMSI Bootloader" - default 0x20 - help - Size of the memory shared between the BSP and the Bootloader in order - to store the GDT. - -endif #SOC_QUARK_SE_C1000_X86 diff --git a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.curie b/soc/x86/intel_quark/quark_se/Kconfig.defconfig.curie deleted file mode 100644 index 61be0e808f3..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.curie +++ /dev/null @@ -1,14 +0,0 @@ -# Kconfig - Curie configuration options - -# -# Copyright (c) 2015-2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_QUARK_SE_CURIE - -config SOC - default "curie" - -endif diff --git a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.quark_se_c1000 b/soc/x86/intel_quark/quark_se/Kconfig.defconfig.quark_se_c1000 deleted file mode 100644 index 583654e3c07..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.quark_se_c1000 +++ /dev/null @@ -1,24 +0,0 @@ -# Kconfig - Quark SE configuration options - -# -# Copyright (c) 2015-2016 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_QUARK_SE_C1000 - -config SOC - default "quark_se_c1000" - -if IEEE802154 && NET_CONFIG_SETTINGS - -config IEEE802154_CC2520 - default y - -config NET_CONFIG_IEEE802154_DEV_NAME - default IEEE802154_CC2520_DRV_NAME - -endif # IEEE802154 && NET_CONFIG_SETTINGS - -endif diff --git a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series b/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series deleted file mode 100644 index 7890bc9d359..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series +++ /dev/null @@ -1,195 +0,0 @@ -# -# Copyright (c) 2016 Intel Corporation Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_QUARK_SE - -config SOC_SERIES - default "quark_se" - -config X86_IAMCU - default y - -config X86_MULTIBOOT - default n - -config X86_NO_MELTDOWN - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32000000 - -config IOAPIC_NUM_RTES - default 64 if IOAPIC - -config LOAPIC_TIMER_IRQ - default 64 if LOAPIC_TIMER - -config QMSI - def_bool y - -if PWM -config PWM_QMSI - default y -endif - -if PINMUX -config PINMUX_QMSI - default y -endif - -if GPIO -config GPIO_QMSI - default y - -config GPIO_QMSI_0 - default y - -config GPIO_QMSI_1 - default y -endif # GPIO - -if I2C -config I2C_QMSI - default y - -config I2C_0 - default y - -config I2C_1 - default y - -config I2C_SDA_SETUP - default 2 - -config I2C_SDA_TX_HOLD - default 16 - -config I2C_SDA_RX_HOLD - default 24 - -endif # I2C - - -if CLOCK_CONTROL - -config CLOCK_CONTROL_QUARK_SE - default y - -if CLOCK_CONTROL_QUARK_SE - -config CLOCK_CONTROL_QUARK_SE_PERIPHERAL - default y -config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME - default "clk_peripheral" - -config CLOCK_CONTROL_QUARK_SE_EXTERNAL - default y -config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME - default "clk_external" - -config CLOCK_CONTROL_QUARK_SE_SENSOR - default y -config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME - default "clk_sensor" - -endif # CLOCK_CONTROL_QUARK_SE - -endif # CLOCK_CONTROL - - -if COUNTER -config AON_COUNTER_QMSI - default y -config AON_TIMER_QMSI - default y -config AON_TIMER_IRQ_PRI - default 2 - -endif - - -if SPI -config SPI_DW - default y - -config SPI_0 - default y - -config SPI_1 - default y - -config SPI_DW_FIFO_DEPTH - default 7 - -if SPI_SLAVE - -config SPI_2 - default y - -config SPI_2_OP_MODES - default 2 - -endif # SPI_SLAVE - -endif # SPI - - -if AIO_COMPARATOR -config AIO_COMPARATOR_QMSI - default y -endif - - -if WATCHDOG -config WDT_QMSI - default y -endif # WATCHDOG - -if COUNTER -config RTC_QMSI - default y -endif # RTC - -if BT_H4 - -config UART_QMSI_0 - default y - -config UART_QMSI_0_HW_FC - default y - -endif # BT_H4 - -if UART_QMSI - -config UART_QMSI_1 - default y - -endif # UART_QMSI - -if SOC_FLASH_QMSI -config SOC_FLASH_QMSI_SYS_SIZE - default 0x60000 -endif # SOC_FLASH_QMSI - -if DMA -config DMA_QMSI - default y -endif - -if USB -config USB_DW - default y -config GPIO - default y -config USB_DW_IRQ_PRI - default 3 -endif # USB - -source "soc/x86/intel_quark/quark_se/Kconfig.defconfig.quark_se*" -source "soc/x86/intel_quark/quark_se/Kconfig.defconfig.curie*" - -endif # SOC_SERIES_QUARK_SE diff --git a/soc/x86/intel_quark/quark_se/Kconfig.series b/soc/x86/intel_quark/quark_se/Kconfig.series deleted file mode 100644 index 18ed2d5441a..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2016 Intel Corporation Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_QUARK_SE - bool "Quark SE Series MCU" - select SOC_FAMILY_QUARK - select CPU_MINUTEIA - select IOAPIC - select LOAPIC - select LOAPIC_TIMER - select XIP - select HAS_SYS_POWER_STATE_SLEEP_1 - select HAS_SYS_POWER_STATE_SLEEP_2 - select HAS_SYS_POWER_STATE_SLEEP_3 - select HAS_SYS_POWER_STATE_DEEP_SLEEP_1 - select HAS_SYS_POWER_STATE_DEEP_SLEEP_2 - select BOOTLOADER_CONTEXT_RESTORE_SUPPORTED - select HAS_QMSI - help - Enable support for Quark SE diff --git a/soc/x86/intel_quark/quark_se/Kconfig.soc b/soc/x86/intel_quark/quark_se/Kconfig.soc deleted file mode 100644 index 2bdd5a002bf..00000000000 --- a/soc/x86/intel_quark/quark_se/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2016 Intel Corporation Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# -choice - prompt "Quark SE Selection" - depends on SOC_SERIES_QUARK_SE - -config SOC_QUARK_SE_C1000 - bool "Intel Quark SE C1000" - select HAS_SPI_DW - -config SOC_QUARK_SE_CURIE - bool "Intel Curie" - select HAS_SPI_DW - -endchoice diff --git a/soc/x86/intel_quark/quark_se/dts_fixup.h b/soc/x86/intel_quark/quark_se/dts_fixup.h deleted file mode 100644 index ce027dce8ff..00000000000 --- a/soc/x86/intel_quark/quark_se/dts_fixup.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/* SoC level DTS fixup file */ - -#define DT_UART_QMSI_0_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002000_CLOCKS_CLOCK_FREQUENCY -#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED -#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL -#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 -#define DT_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY -#define DT_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE - -#define DT_UART_QMSI_1_CLOCK_FREQUENCY DT_INTEL_QMSI_UART_B0002400_CLOCKS_CLOCK_FREQUENCY -#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED -#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL -#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 -#define DT_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY -#define DT_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE - -#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS - -#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS - -#define DT_RAM_SIZE CONFIG_SRAM_SIZE - -#define DT_ROM_SIZE CONFIG_FLASH_SIZE - -#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS - -#define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL -#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY -#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 -#define DT_I2C_0_IRQ_PRI DT_INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY -#define DT_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE -#define CONFIG_I2C_1_NAME DT_INTEL_QMSI_I2C_B0002C00_LABEL -#define DT_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY -#define DT_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 -#define DT_I2C_1_IRQ_PRI DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY -#define DT_I2C_1_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_SENSE - -#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL -#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 -#define DT_GPIO_QMSI_0_IRQ_PRI DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY -#define DT_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE -#define DT_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL -#define DT_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 -#define DT_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY -#define DT_GPIO_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_SENSE - -#define DT_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL -#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 -#define DT_RTC_0_IRQ_PRI DT_INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY -#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE - -#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS -#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001000_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL -#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 -#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY - -#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS -#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001400_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL -#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 -#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY - -#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS -#define DT_SPI_2_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001800_CLOCKS_CLOCK_FREQUENCY -#define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL -#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 -#define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY - -#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL -#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 -#define DT_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY -#define DT_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE - -/* End of SoC Level DTS fixup file */ diff --git a/soc/x86/intel_quark/quark_se/eoi.c b/soc/x86/intel_quark/quark_se/eoi.c deleted file mode 100644 index 523e49f03dd..00000000000 --- a/soc/x86/intel_quark/quark_se/eoi.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Code to compensate for Lakemont EOI forwarding bug - * - * Lakemont CPU on Quark SE has a bug where LOAPIC EOI does not - * correctly forward EOI to the IOAPIC, causing the IRR bit in the RTE - * to never get cleared. We need to set the IOAPIC EOI register manually - * with the vector of the interrupt. - */ - -#include -#include -#include -#include - -void z_lakemont_eoi(void) -{ - /* It is difficult to know whether the IRQ being serviced is - * a level interrupt handled by the IOAPIC; the only information - * we have is the vector # in the IDT. So unconditionally - * write to IOAPIC_EOI for every interrupt - */ - sys_write32(z_irq_controller_isr_vector_get(), - DT_IOAPIC_BASE_ADDRESS + IOAPIC_EOI); - - /* Send EOI to the LOAPIC as well */ - sys_write32(0, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI); -} - diff --git a/soc/x86/intel_quark/quark_se/linker.ld b/soc/x86/intel_quark/quark_se/linker.ld deleted file mode 100644 index eca933f8fe1..00000000000 --- a/soc/x86/intel_quark/quark_se/linker.ld +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * This is the linker script for both standard images and XIP images. - */ - -#include - -#include -/* physical address of RAM (needed for correct __ram_phys_end symbol) */ -#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR - -/* physical address where the kernel is loaded */ -#ifdef CONFIG_XIP - #define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR -#else /* !CONFIG_XIP */ - #define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR -#endif /* CONFIG_XIP */ - -/* total shared RAM size (restore info + gdt) */ -#define BSP_SHARED_RAM_SIZE \ - (CONFIG_SHARED_GDT_RAM_SIZE+CONFIG_BSP_SHARED_RESTORE_INFO_SIZE) -/* - * When DEEP_SLEEP is not enabled, the shared memory can be re-used after boot. - * Since the memory regions area are at fixed address locations, only the - * contiguous unused memory located at the end of RAM should be made available. - */ -#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES -#define PHYS_RAM_SIZE DT_RAM_SIZE*1K - BSP_SHARED_RAM_SIZE -#else -#ifdef CONFIG_SET_GDT -#define PHYS_RAM_SIZE DT_RAM_SIZE*1K -#else -#define PHYS_RAM_SIZE DT_RAM_SIZE*1K - CONFIG_SHARED_GDT_RAM_SIZE -#endif -#endif - -MEMORY - { -#ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE -#else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE -#endif /* CONFIG_XIP */ -#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES - BSP_SHARED_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR, - LENGTH = CONFIG_BSP_SHARED_RESTORE_INFO_SIZE -#endif /* CONFIG_SYS_POWER_DEEP_SLEEP_STATES */ -#ifndef CONFIG_SET_GDT - SHARED_GDT_RAM (rw) : ORIGIN = CONFIG_SHARED_GDT_RAM_ADDR, - LENGTH = CONFIG_SHARED_GDT_RAM_SIZE -#endif /* !CONFIG_SET_GDT */ - - /* - * It doesn't matter where this region goes as it is stripped from the - * final ELF image. The address doesn't even have to be valid on the - * target. However, it shouldn't overlap any other regions. - */ - - IDT_LIST : ORIGIN = 2K, LENGTH = 2K - MMU_LIST : ORIGIN = 4k, LENGTH = 1K - } - -#include - diff --git a/soc/x86/intel_quark/quark_se/power.c b/soc/x86/intel_quark/quark_se/power.c deleted file mode 100644 index b145e30d00e..00000000000 --- a/soc/x86/intel_quark/quark_se/power.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#include "power_states.h" - -#define _REG_TIMER_ICR ((volatile u32_t *) \ - (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR)) - -/* Variables used to save CPU state */ -u64_t _pm_save_gdtr; -u64_t _pm_save_idtr; -u32_t _pm_save_esp; - -extern void z_power_soc_sleep(void); -extern void z_power_restore_cpu_context(void); -extern void z_power_soc_deep_sleep(void); - -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) -static u32_t *__x86_restore_info = - (u32_t *)CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR; - -static void deep_sleep(enum power_states state) -{ - /* - * Setting resume vector inside the restore_cpu_context - * function since we have nothing to do before cpu context - * is restored. If necessary, it is possible to set the - * resume vector to a location where additional processing - * can be done before cpu context is restored and control - * transferred to _sys_suspend. - */ - qm_x86_set_resume_vector(z_power_restore_cpu_context, - *__x86_restore_info); - - qm_power_soc_set_x86_restore_flag(); - - switch (state) { - case SYS_POWER_STATE_DEEP_SLEEP_1: - z_power_soc_sleep(); - break; - case SYS_POWER_STATE_DEEP_SLEEP_2: - z_power_soc_deep_sleep(); - break; - default: - break; - } -} -#endif - -void sys_set_power_state(enum power_states state) -{ - switch (state) { -#if (defined(CONFIG_SYS_POWER_SLEEP_STATES)) - case SYS_POWER_STATE_SLEEP_1: - qm_power_cpu_c1(); - break; - case SYS_POWER_STATE_SLEEP_2: - qm_power_cpu_c2(); - break; - case SYS_POWER_STATE_SLEEP_3: - qm_power_cpu_c2lp(); - break; -#endif -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) - case SYS_POWER_STATE_DEEP_SLEEP_1: - case SYS_POWER_STATE_DEEP_SLEEP_2: - deep_sleep(state); - break; -#endif - default: - break; - } -} - -void _sys_pm_power_state_exit_post_ops(enum power_states state) -{ - switch (state) { -#if (defined(CONFIG_SYS_POWER_SLEEP_STATES)) - case SYS_POWER_STATE_SLEEP_3: - *_REG_TIMER_ICR = 1U; - case SYS_POWER_STATE_SLEEP_2: - case SYS_POWER_STATE_SLEEP_1: - __asm__ volatile("sti"); - break; -#endif -#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) - case SYS_POWER_STATE_DEEP_SLEEP_2: -#ifdef CONFIG_ARC_INIT - z_arc_init(NULL); -#endif /* CONFIG_ARC_INIT */ - /* Fallthrough */ - case SYS_POWER_STATE_DEEP_SLEEP_1: - __asm__ volatile("sti"); - break; -#endif - default: - break; - } -} - -bool sys_power_state_is_arc_ready(void) -{ - return QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY ? true : false; -} diff --git a/soc/x86/intel_quark/quark_se/shared_mem.h b/soc/x86/intel_quark/quark_se/shared_mem.h deleted file mode 100644 index aeca9974612..00000000000 --- a/soc/x86/intel_quark/quark_se/shared_mem.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SHARED_MEM_H_ -#define _SHARED_MEM_H_ - -/* Start of the shared 80K RAM */ -#define SHARED_ADDR_START 0xA8000000 - -struct shared_mem { - u32_t arc_start; - u32_t flags; -}; - -#define ARC_READY (1 << 0) - -#define shared_data ((volatile struct shared_mem *) SHARED_ADDR_START) - -#endif diff --git a/soc/x86/intel_quark/quark_se/soc.c b/soc/x86/intel_quark/quark_se/soc.c deleted file mode 100644 index 8d2f6623aab..00000000000 --- a/soc/x86/intel_quark/quark_se/soc.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for the Quark SE BSP - * - * This module provides routines to initialize and support board-level - * hardware for the Quark SE BSP. - */ - -#include - -#include -#include -#include -#include "soc.h" -#include -#include -#include "shared_mem.h" -#include - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -#include -LOG_MODULE_REGISTER(soc); - -#ifdef CONFIG_X86_MMU -/* loapic */ -MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE); - -/*ioapic */ -MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE); - -/* peripherals */ -MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE); - -/* SCSS system control subsystem */ -MMU_BOOT_REGION(0xB0800000, 16*1024, MMU_ENTRY_WRITE); - -/* DMA */ -MMU_BOOT_REGION(0xB0700000, 4*1024, MMU_ENTRY_WRITE); - -/* USB */ -MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE); - -#endif /* CONFIG_X86_MMU */ - - -#ifdef CONFIG_ARC_INIT -#define SCSS_REG_VAL(offset) \ - (*((volatile u32_t *)(SCSS_REGISTER_BASE+offset))) - -/** - * - * @brief ARC Init - * - * This routine initialize the ARC reset vector and - * starts the ARC processor. - * @return N/A - */ -/* This function is also called at deep sleep resume. */ -int z_arc_init(struct device *arg) -{ - u32_t *reset_vector; - - ARG_UNUSED(arg); - - if (SCSS_REG_VAL(SCSS_SS_STS) == 0U) { - /* ARC shouldn't already be running! */ - printk("ARC core already running!"); - return -EIO; - } - - /* Address of ARC side __reset stored in the first 4 bytes of arc.bin, - * we read the value and stick it in shared_mem->arc_start which is - * the beginning of the address space at 0xA8000000 */ - reset_vector = (u32_t *)RESET_VECTOR; - LOG_DBG("Reset vector address: %x", *reset_vector); - shared_data->arc_start = *reset_vector; - shared_data->flags = 0U; - if (shared_data->arc_start == 0U) { - /* Reset vector points to NULL => skip ARC init. */ - LOG_DBG("Reset vector is NULL, skipping ARC init."); - goto skip_arc_init; - } - -#ifndef CONFIG_ARC_GDB_ENABLE - /* Start the CPU */ - SCSS_REG_VAL(SCSS_SS_CFG) |= ARC_RUN_REQ_A; -#endif - - LOG_DBG("Waiting for arc to start..."); - /* Block until the ARC core actually starts up */ - while ((SCSS_REG_VAL(SCSS_SS_STS) & 0x4000) != 0U) { - } - - /* Block until ARC's quark_se_init() sets a flag indicating it is ready, - * if we get stuck here ARC has run but has exploded very early */ - LOG_DBG("Waiting for arc to init..."); - while ((shared_data->flags & ARC_READY) == 0U) { - } - -skip_arc_init: - - return 0; -} - -SYS_INIT(z_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - -#endif /*CONFIG_ARC_INIT*/ - diff --git a/soc/x86/intel_quark/quark_se/soc.h b/soc/x86/intel_quark/quark_se/soc.h deleted file mode 100644 index de3592e9f9d..00000000000 --- a/soc/x86/intel_quark/quark_se/soc.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief board configuration macros for the Quark SE - * This header file is used to specify and describe board-level aspects for - * the Quark SE Platform. - */ - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include -#include -#include - -#ifdef CONFIG_IOAPIC -#include -#endif - -#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */ - -#ifndef _ASMLANGUAGE - -/* Base Register */ -#define SCSS_REGISTER_BASE 0xB0800000 - -#define INT_UNMASK_IA (~0x00000001) - -/* Clock */ -#define CLOCK_PERIPHERAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x18) -#define CLOCK_EXTERNAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x24) -#define CLOCK_SENSOR_BASE_ADDR (SCSS_REGISTER_BASE + 0x28) -#define CLOCK_SYSTEM_CLOCK_CONTROL (SCSS_REGISTER_BASE + SCSS_CCU_SYS_CLK_CTL) - -/* ARC INIT */ -#define RESET_VECTOR CONFIG_SS_RESET_VECTOR -#define SCSS_SS_CFG 0x0600 -#define SCSS_SS_STS 0x0604 -#define ARC_HALT_INT_REDIR (1 << 26) -#define ARC_HALT_REQ_A (1 << 25) -#define ARC_RUN_REQ_A (1 << 24) -#define ARC_RUN (ARC_HALT_INT_REDIR | ARC_RUN_REQ_A) -#define ARC_HALT (ARC_HALT_INT_REDIR | ARC_HALT_REQ_A) - -/* The CPU-visible IRQ numbers change between the ARC and IA cores, - * and QMSI itself has no easy way to pick the correct one, though it - * does have the necessary information to do it ourselves (in the meantime). - * This macro will be used by the shim drivers to get the IRQ number to - * use, and it should always be called using the QM_IRQ_*_INT macro - * provided by QMSI. - */ -#define IRQ_GET_NUMBER(_irq) _irq - -/* - * PINMUX configuration settings - */ -#define PINMUX_BASE_ADDR 0xb0800900 - -#define UART_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) - -#ifdef CONFIG_SPI_DW - -#define SPI_DW_PORT_0_INT_MASK (SCSS_REGISTER_BASE + 0x454) - -#define SPI_DW_PORT_1_INT_MASK (SCSS_REGISTER_BASE + 0x458) - -#define SPI_DW_PORT_2_INT_MASK (SCSS_REGISTER_BASE + 0x45C) - -#define DT_SPI_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) - -#endif /* CONFIG_SPI_DW */ - -#ifdef CONFIG_USB_DW - -#define USB_DW_BASE QM_USB_0_BASE -#define USB_DW_IRQ QM_IRQ_USB_0_INT - -#endif - -#endif /* _ASMLANGUAGE */ - -#ifdef CONFIG_ARC_INIT -int z_arc_init(struct device *arg); -#endif /* CONFIG_ARC_INIT */ - -#endif /* __SOC_H_ */ diff --git a/soc/x86/intel_quark/quark_se/soc_config.c b/soc/x86/intel_quark/quark_se/soc_config.c deleted file mode 100644 index 651383cf1d9..00000000000 --- a/soc/x86/intel_quark/quark_se/soc_config.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2015 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include -#include - -#if CONFIG_IPM_QUARK_SE -#include -#include - -static int x86_quark_se_ipm_init(void) -{ - IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_IPM_IRQ_PRI, - quark_se_ipm_isr, NULL, 0); - irq_enable(QUARK_SE_IPM_INTERRUPT); - return 0; -} - -static struct quark_se_ipm_controller_config_info ipm_controller_config = { - .controller_init = x86_quark_se_ipm_init -}; -DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize, - NULL, &ipm_controller_config, - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, - &ipm_quark_se_api_funcs); - -#if defined(CONFIG_IPM_CONSOLE_RECEIVER) && defined(CONFIG_PRINTK) -#include - -QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_INBOUND); - -#define QUARK_SE_IPM_CONSOLE_LINE_BUF_SIZE 80 - -static u32_t ipm_console_ring_buf_data[CONFIG_QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32]; -static K_THREAD_STACK_DEFINE(ipm_console_thread_stack, CONFIG_IPM_CONSOLE_STACK_SIZE); -static char ipm_console_line_buf[QUARK_SE_IPM_CONSOLE_LINE_BUF_SIZE]; - -static struct ipm_console_receiver_config_info quark_se_ipm_receiver_config = { - .bind_to = "quark_se_ipm4", - .thread_stack = ipm_console_thread_stack, - .ring_buf_data = ipm_console_ring_buf_data, - .rb_size32 = CONFIG_QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32, - .line_buf = ipm_console_line_buf, - .lb_size = QUARK_SE_IPM_CONSOLE_LINE_BUF_SIZE, - .flags = IPM_CONSOLE_PRINTK -}; -struct ipm_console_receiver_runtime_data quark_se_ipm_receiver_driver_data; -DEVICE_INIT(ipm_console0, "ipm_console0", ipm_console_receiver_init, - &quark_se_ipm_receiver_driver_data, &quark_se_ipm_receiver_config, - POST_KERNEL, CONFIG_IPM_CONSOLE_INIT_PRIORITY); - -#endif /* CONFIG_PRINTK && CONFIG_IPM_CONSOLE_RECEIVER */ -#endif /* CONFIG_IPM_QUARK_SE */ diff --git a/soc/x86/intel_quark/quark_se/soc_power.S b/soc/x86/intel_quark/quark_se/soc_power.S deleted file mode 100644 index c919072c2ef..00000000000 --- a/soc/x86/intel_quark/quark_se/soc_power.S +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES -GDATA(_pm_save_gdtr) -GDATA(_pm_save_idtr) -GDATA(_pm_save_esp) - -GTEXT(sys_resume_from_deep_sleep) -GTEXT(z_power_restore_cpu_context) -GTEXT(z_power_soc_sleep) -GTEXT(z_power_soc_deep_sleep) - -SECTION_FUNC(TEXT, save_cpu_context) - movl %esp, %eax /* save ptr to return address */ - - pushf /* save flags */ - pusha /* save GPRs */ -#if defined (CONFIG_DEBUG) - /* save the debug registers */ - movl %dr0, %edx - pushl %edx - movl %dr1, %edx - pushl %edx - movl %dr2, %edx - pushl %edx - movl %dr3, %edx - pushl %edx - movl %dr6, %edx - pushl %edx - movl %dr7, %edx - pushl %edx -#endif - movl %esp, _pm_save_esp /* save stack ptr */ - sidtl _pm_save_idtr /* save idtr */ - sgdtl _pm_save_gdtr /* save gdtr */ - - pushl (%eax) /* push return address */ - ret - -SECTION_FUNC(TEXT, z_power_restore_cpu_context) - lgdtl _pm_save_gdtr /* restore gdtr */ - lidtl _pm_save_idtr /* restore idtr */ - movl _pm_save_esp, %esp /* restore saved stack ptr */ -#if defined (CONFIG_DEBUG) - /* restore the debug registers */ - popl %edx - movl %edx, %dr7 - popl %edx - movl %edx, %dr6 - popl %edx - movl %edx, %dr3 - popl %edx - movl %edx, %dr2 - popl %edx - movl %edx, %dr1 - popl %edx - movl %edx, %dr0 -#endif - popa /* restore saved GPRs */ - popf /* restore saved flags */ - - /* - * At this point the stack contents will be as follows: - * - * Saved context - * ESP ---> Return address of save_cpu_context - * Return address of z_power_soc_sleep/deep_sleep - * - * We just popped the saved context. Next we pop out the address - * of the caller of save_cpu_context.Then the ret would return - * to caller of z_power_soc_sleep or z_power_soc_deep_sleep. - * - */ - addl $4, %esp - ret - -SECTION_FUNC(TEXT, z_power_soc_sleep) - call save_cpu_context - wbinvd - call qm_power_soc_sleep - /* Does not return */ - -SECTION_FUNC(TEXT, z_power_soc_deep_sleep) - call save_cpu_context - wbinvd - call qm_power_soc_deep_sleep - /* Does not return */ - -/* - * This is an example function to handle the deep sleep resume notification - * in the absence of bootloader context restore support. - * - * Bootloader in Intel Quark SE Microcontroller C1000 boards have - * context restore support and this would not be required. - * - * Disclaimer: This can be used for debug or development purposes. This is not - * a supported feature in Quark SE boards and to be used at one's own risk. - */ -SECTION_FUNC(TEXT, _sys_resume_from_deep_sleep) - movl $CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR, %eax - cmpl $z_power_restore_cpu_context, (%eax) - je z_power_restore_cpu_context - ret - -#endif diff --git a/soc/x86/intel_quark/quark_se/soc_power.h b/soc/x86/intel_quark/quark_se/soc_power.h deleted file mode 100644 index 521236c125e..00000000000 --- a/soc/x86/intel_quark/quark_se/soc_power.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC_POWER_H_ -#define _SOC_POWER_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Bit 0 from GP0 register is used internally by the kernel - * to handle PM multicore support. Any change on QMSI and/or - * bootloader which affects this bit should take it in - * consideration. - */ -#define GP0_BIT_SLEEP_READY BIT(0) - -/* - * Power state map: - * SYS_POWER_STATE_SLEEP_1: C1 state - * SYS_POWER_STATE_SLEEP_2: C2 state - * SYS_POWER_STATE_SLEEP_3: C2LP state - * SYS_POWER_STATE_DEEP_SLEEP_1: SLEEP state - * SYS_POWER_STATE_DEEP_SLEEP_2: SLEEP state with LPMODE enabled - */ - -/** - * @brief Check if ARC core is ready to enter in DEEP_SLEEP states. - * - * @retval true If ARC is ready. - * @retval false Otherwise. - */ -bool sys_power_state_is_arc_ready(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_POWER_H_ */ diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 9f6c20238f4..acb0f7dd70e 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -102,16 +102,6 @@ #define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT #define ADC_1ST_CHANNEL_ID 0 -#elif defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS) || \ - defined(CONFIG_BOARD_ARDUINO_101_SSS) -#define ADC_DEVICE_NAME DT_ADC_0_NAME -#define ADC_RESOLUTION 10 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 10 -#define ADC_2ND_CHANNEL_ID 11 - #elif defined(CONFIG_SOC_FAMILY_SAM0) #include #define ADC_DEVICE_NAME DT_INST_0_ATMEL_SAM0_ADC_LABEL diff --git a/tests/drivers/aio/api/CMakeLists.txt b/tests/drivers/aio/api/CMakeLists.txt deleted file mode 100644 index b13f54b73b0..00000000000 --- a/tests/drivers/aio/api/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(aio_api) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/aio/api/prj.conf b/tests/drivers/aio/api/prj.conf deleted file mode 100644 index 4300f424d5a..00000000000 --- a/tests/drivers/aio/api/prj.conf +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_GPIO=y -CONFIG_PINMUX=y -CONFIG_AIO_COMPARATOR=y -CONFIG_AIO_COMPARATOR_QMSI=y -CONFIG_ZTEST=y diff --git a/tests/drivers/aio/api/src/main.c b/tests/drivers/aio/api/src/main.c deleted file mode 100644 index 2e5ecd83ced..00000000000 --- a/tests/drivers/aio/api/src/main.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @addtogroup t_driver_aio - * @{ - * @defgroup t_aio_basic_api test_aio_basic_api - * @} - * - * Setup: loop PIN_OUT with PIN_IN on target board - * - * quark_se_c1000_devboard - x86 - * ------------------------ - * 1. PIN_OUT is GPIO_15 - * 2. PIN_IN is AIN_10 - * - * quark_se_c1000_ss_evboard - arc - * ------------------------ - * 1. PIN_OUT is GPIO_SS_3 - * 2. PIN_IN is AIN_10 - */ - -#include - -extern void test_aio_callback_rise(void); -extern void test_aio_callback_fall(void); -extern void test_aio_callback_rise_disable(void); - -void test_main(void) -{ - ztest_test_suite(aio_basic_api_test, - ztest_unit_test(test_aio_callback_rise), - ztest_unit_test(test_aio_callback_fall), - ztest_unit_test(test_aio_callback_rise_disable)); - ztest_run_test_suite(aio_basic_api_test); -} diff --git a/tests/drivers/aio/api/src/test_callback.c b/tests/drivers/aio/api/src/test_callback.c deleted file mode 100644 index e4e7f543bd0..00000000000 --- a/tests/drivers/aio/api/src/test_callback.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#define AIO_CMP_DEV_NAME CONFIG_AIO_COMPARATOR_0_NAME -#define PINMUX_NAME CONFIG_PINMUX_NAME - -#ifdef CONFIG_ARC -#define GPIO_DEV_NAME DT_GPIO_QMSI_SS_0_NAME -#else -#define GPIO_DEV_NAME DT_GPIO_QMSI_0_NAME -#endif - -#if defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) -#define PIN_OUT 15 /* GPIO15 */ -#define PIN_IN 10 /* GPIO_SS_AIN_10 */ -#elif defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS) -#define PIN_OUT 3 /* GPIO_SS_3 */ -#define PIN_IN 10 /* GPIO_SS_AIN_10 */ -#elif defined(CONFIG_BOARD_ARDUINO_101) -#define PIN_OUT 16 /* GPIO_16 */ -#define PIN_IN 10 /* AIN_10 */ -#elif defined(CONFIG_BOARD_ARDUINO_101_SSS) -#define PIN_OUT 3 /* GPIO_SS_3 */ -#define PIN_IN 10 /* AIN_10 */ -#endif - -volatile int cb_cnt; -static struct device *aio_dev; -static struct device *gpio_dev; - -static void callback(void *param) -{ - int polarity = *(int *)param; - - cb_cnt++; - TC_PRINT("*** callback triggered %s\n", - (polarity == AIO_CMP_POL_RISE) ? "rising" : "falling" - ); - - if (polarity == AIO_CMP_POL_FALL) { - gpio_pin_write(gpio_dev, PIN_OUT, 1); - } else { - gpio_pin_write(gpio_dev, PIN_OUT, 0); - } - - if (aio_cmp_get_pending_int(aio_dev)) { - TC_PRINT("Catch aio_cmp pending interrupt\n"); - } else { - TC_PRINT("Fail to catch aio_cmp pending interrupt\n"); - } - - aio_cmp_disable(aio_dev, PIN_IN); -} - -static int set_aio_callback(int polarity, int disable) -{ - struct device *pinmux = device_get_binding(PINMUX_NAME); - - if (!pinmux) { - TC_PRINT("Cannot get PINMUX\n"); - return TC_FAIL; - } - - aio_dev = device_get_binding(AIO_CMP_DEV_NAME); - if (!aio_dev) { - TC_PRINT("AIO Device binding failed\n"); - return TC_FAIL; - } - - gpio_dev = device_get_binding(GPIO_DEV_NAME); - if (!gpio_dev) { - TC_PRINT("GPIO Device binding failed\n"); - return TC_FAIL; - } - - if (gpio_pin_configure(gpio_dev, PIN_OUT, GPIO_DIR_OUT)) { - TC_PRINT("Fail to configure GPIO Pin %d\n", PIN_OUT); - return TC_FAIL; - } - - if (pinmux_pin_set(pinmux, PIN_IN, PINMUX_FUNC_B)) { - TC_PRINT("Fail to set pin func, %u\n", PIN_IN); - return TC_FAIL; - } - - gpio_pin_write(gpio_dev, PIN_OUT, - (polarity == AIO_CMP_POL_RISE) ? 0 : 1); - - /* config AIN callback */ - zassert_true(aio_cmp_configure(aio_dev, PIN_IN, - polarity, AIO_CMP_REF_B, - callback, (void *)aio_dev) == 0, - "ERROR registering callback"); - if (disable == 1) { - if (aio_cmp_disable(aio_dev, PIN_IN)) { - TC_PRINT("Fail to disable callback\n"); - return TC_FAIL; - } - } - - k_sleep(100); - cb_cnt = 0; - k_sleep(100); - - gpio_pin_write(gpio_dev, PIN_OUT, - (polarity == AIO_CMP_POL_RISE) ? 1 : 0); - - k_sleep(1000); - TC_PRINT("... cb_cnt = %d\n", cb_cnt); - - return TC_PASS; -} - -void test_aio_callback_rise(void) -{ - set_aio_callback(AIO_CMP_POL_RISE, 0); - zassert_true(cb_cnt == 1, "callback is not invoked correctly"); -} - -void test_aio_callback_fall(void) -{ - set_aio_callback(AIO_CMP_POL_FALL, 0); - zassert_true(cb_cnt == 1, "callback is not invoked correctly"); -} - -void test_aio_callback_rise_disable(void) -{ - set_aio_callback(AIO_CMP_POL_RISE, 1); - zassert_true(cb_cnt == 0, "callback is not invoked correctly"); -} diff --git a/tests/drivers/aio/api/testcase.yaml b/tests/drivers/aio/api/testcase.yaml deleted file mode 100644 index 7e1da7eb308..00000000000 --- a/tests/drivers/aio/api/testcase.yaml +++ /dev/null @@ -1,5 +0,0 @@ -tests: - peripheral.aio: - depends_on: aio - harness: aio - tags: aio diff --git a/tests/drivers/aio/app/CMakeLists.txt b/tests/drivers/aio/app/CMakeLists.txt deleted file mode 100644 index fe109a9d07d..00000000000 --- a/tests/drivers/aio/app/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(aio_app) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/aio/app/prj.conf b/tests/drivers/aio/app/prj.conf deleted file mode 100644 index 17a900fb55d..00000000000 --- a/tests/drivers/aio/app/prj.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_TEST=y -CONFIG_STDOUT_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_AIO_COMPARATOR=y diff --git a/tests/drivers/aio/app/src/main.c b/tests/drivers/aio/app/src/main.c deleted file mode 100644 index 256f5e6a61a..00000000000 --- a/tests/drivers/aio/app/src/main.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief DesignWare AIO/Comparator demo on Arduino 101 - * - * This is used to demo the DesignWare AIO/Comparator. The voltage input - * pin is analog in A0 on circuit board, which maps to AIN[10] on chip. - * - * The comparison is using the internal 3.3V as reference voltage, - * so it needs a higher voltage to trigger comparator. - * - * To test: - * 1. Connect the A0 pin to ground via a resistor. Any larger than - * 1k Ohm would be fine. This is to avoid floating pin. - * 2. Turn on the device. - * 3. Wait for device to boot, until "app started" line appeared. - * 4. Connect a voltage source higher than 3.3V (the 5V line would work). - * The line "*** A0, AIN[10] triggered rising." should appear. - * 5. Remove the voltage source. - * The line "*** A0, AIN[10] triggered falling." should appear. - */ - -#include -#include -#include -#include -#include - -/* specify delay between greetings (in ms) */ -#define SLEEPTIME 5000 - -struct cb_data_t { - u8_t ain_idx; - enum aio_cmp_ref ref; - enum aio_cmp_polarity pol; - char name[50]; -}; - -static struct cb_data_t cb_data = { - .ain_idx = 10, - .ref = AIO_CMP_REF_A, - .pol = AIO_CMP_POL_RISE, - .name = "A0, AIN[10]", -}; - -static void cb(void *param) -{ - struct device *aio_cmp_dev; - struct cb_data_t *p = (struct cb_data_t *)param; - - aio_cmp_dev = device_get_binding(CONFIG_AIO_COMPARATOR_0_NAME); - - printf("*** %s triggered %s.\n", p->name, - (p->pol == AIO_CMP_POL_RISE) ? "rising" : "falling"); - - if (p->pol == AIO_CMP_POL_RISE) { - p->pol = AIO_CMP_POL_FALL; - } else { - p->pol = AIO_CMP_POL_RISE; - } - - aio_cmp_configure(aio_cmp_dev, p->ain_idx, p->pol, p->ref, cb, p); -} - -void main(void) -{ - struct device *aio_cmp_dev; - int i, ret; - int cnt = 0; - - aio_cmp_dev = device_get_binding(CONFIG_AIO_COMPARATOR_0_NAME); - if (!aio_cmp_dev) { - printf("AIO device driver not found\n"); - return; - } - - printf("===== app started ========\n"); - - for (i = 0; i < 4; i++) { - /* REF_A is to use AREF for reference */ - ret = aio_cmp_configure(aio_cmp_dev, cb_data.ain_idx, - cb_data.pol, cb_data.ref, - cb, &cb_data); - if (ret) { - printf("ERROR registering callback for %s (%d)\n", - cb_data.name, ret); - } - } - - while (1) { - printf("... waiting for event! (%d)\n", ++cnt); - - /* wait a while */ - k_sleep(SLEEPTIME); - } -} - diff --git a/tests/drivers/aio/app/testcase.yaml b/tests/drivers/aio/app/testcase.yaml deleted file mode 100644 index ca0ef5307e2..00000000000 --- a/tests/drivers/aio/app/testcase.yaml +++ /dev/null @@ -1,5 +0,0 @@ -tests: - peripheral.aio: - tags: aio - harness: aio - depends_on: aio diff --git a/tests/drivers/ipm/testcase.yaml b/tests/drivers/ipm/testcase.yaml index 469feaf29cf..c3092e54394 100644 --- a/tests/drivers/ipm/testcase.yaml +++ b/tests/drivers/ipm/testcase.yaml @@ -1,6 +1,5 @@ tests: peripheral.mailbox: - filter: not CONFIG_SOC_QUARK_SE_C1000_SS arch_exclude: posix xtensa platform_exclude: qemu_x86_64 # see issue #12478 tags: drivers ipc diff --git a/tests/drivers/spi/spi_loopback/boards/quark_se_c1000_devboard.conf b/tests/drivers/spi/spi_loopback/boards/quark_se_c1000_devboard.conf deleted file mode 100644 index c601c2ea191..00000000000 --- a/tests/drivers/spi/spi_loopback/boards/quark_se_c1000_devboard.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_GPIO=y -CONFIG_SPI_DW=y -CONFIG_SPI_LOOPBACK_SLOW_FREQ=128000 -CONFIG_SPI_LOOPBACK_SLAVE_NUMBER=1 diff --git a/tests/kernel/tickless/tickless/src/main.c b/tests/kernel/tickless/tickless/src/main.c index 4378be014e8..03e3fad9b6a 100644 --- a/tests/kernel/tickless/tickless/src/main.c +++ b/tests/kernel/tickless/tickless/src/main.c @@ -186,7 +186,7 @@ void ticklessTestThread(void) #elif defined(CONFIG_ARCH_POSIX) printk("diff time stamp: %llu\n", diff_tsc); printk("Cal time stamp: %llu\n", cal_tsc); -#elif defined(CONFIG_ARM) || defined(CONFIG_SOC_QUARK_SE_C1000_SS) +#elif defined(CONFIG_ARM) printk("diff time stamp: 0x%x\n", diff_tsc); printk("Cal time stamp: 0x%x\n", cal_tsc); #endif diff --git a/tests/kernel/tickless/tickless/testcase.yaml b/tests/kernel/tickless/tickless/testcase.yaml index 9de1ea2f8fb..2434b94df8d 100644 --- a/tests/kernel/tickless/tickless/testcase.yaml +++ b/tests/kernel/tickless/tickless/testcase.yaml @@ -2,6 +2,5 @@ tests: kernel.tickless: arch_exclude: nios2 riscv32 filter: CONFIG_X86 or (CONFIG_ARM and (CONFIG_SOC_MK64F12 - or CONFIG_SOC_SERIES_SAM3X)) or (CONFIG_ARC and - CONFIG_SOC_QUARK_SE_C1000_SS) or CONFIG_ARCH_POSIX + or CONFIG_SOC_SERIES_SAM3X)) or CONFIG_ARCH_POSIX tags: tickless kernel diff --git a/tests/net/ieee802154/crypto/CMakeLists.txt b/tests/net/ieee802154/crypto/CMakeLists.txt deleted file mode 100644 index 1195a68ef66..00000000000 --- a/tests/net/ieee802154/crypto/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(crypto) - -target_include_directories( - app - PRIVATE - $ENV{ZEPHYR_BASE}/subsys/net/ip - $ENV{ZEPHYR_BASE}/subsys/net/l2/ieee802154 - ) -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/net/ieee802154/crypto/prj.conf b/tests/net/ieee802154/crypto/prj.conf deleted file mode 100644 index 3d9abf48d6c..00000000000 --- a/tests/net/ieee802154/crypto/prj.conf +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_ZTEST=y - -CONFIG_NETWORKING=y -CONFIG_TEST_RANDOM_GENERATOR=y - -CONFIG_NET_PKT_RX_COUNT=6 -CONFIG_NET_PKT_TX_COUNT=6 - -CONFIG_NET_IPV4=n -CONFIG_NET_IPV6=y -CONFIG_NET_IPV6_RA_RDNSS=y -CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=2 - -CONFIG_NET_LOG=y -CONFIG_INIT_STACKS=y -CONFIG_PRINTK=y - -CONFIG_NET_STATISTICS=y - -CONFIG_NET_L2_IEEE802154=y -CONFIG_NET_L2_IEEE802154_RFD=y - -CONFIG_IEEE802154_CC2520=y - -CONFIG_NET_L2_IEEE802154_SHELL=y - -CONFIG_NET_L2_IEEE802154_SECURITY=y -CONFIG_IEEE802154_CC2520_CRYPTO=y diff --git a/tests/net/ieee802154/crypto/src/ieee802154_crypto_test.c b/tests/net/ieee802154/crypto/src/ieee802154_crypto_test.c deleted file mode 100644 index 123436146b5..00000000000 --- a/tests/net/ieee802154/crypto/src/ieee802154_crypto_test.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -LOG_MODULE_REGISTER(net_test, LOG_LEVEL_DBG); - -#include -#include -#include - -#include - -#include -#include - -#ifdef CONFIG_IEEE802154_CC2520_CRYPTO_DRV_NAME -#define IEEE802154_CRYPTO_DRV_NAME CONFIG_IEEE802154_CC2520_CRYPTO_DRV_NAME -#endif - -struct cipher_ctx enc; -struct cipher_ctx dec; -struct cipher_pkt pkt; -struct cipher_aead_pkt apkt; -u8_t buf[128]; - -static void print_caps(struct device *dev) -{ - int caps = cipher_query_hwcaps(dev); - - printk("Crypto hardware capabilities:\n"); - - if (caps & CAP_RAW_KEY) { - printk("\tCAPS_RAW_KEY\n"); - } - - if (caps & CAP_INPLACE_OPS) { - printk("\tCAP_INPLACE_OPS\n"); - } - - if (caps & CAP_SYNC_OPS) { - printk("\tCAP_SYNC_OPS\n"); - } -} - -static void print_buffer(u8_t *buf, u8_t len) -{ - int i; - - printk("Buffer content:\n"); - - printk("\t"); - - for (i = 0; len > 0; len--, i++) { - printk("%02x ", *buf++); - - if (i == 7) { - printk("\n\t"); - i = -1; - } - } - - printk("\n"); -} - -static bool verify_result(u8_t *result, int result_len, - u8_t *verify, int verify_len) -{ - if (result_len != verify_len) { - NET_ERR("Result and verification length don't match (%i vs %i)", - result_len, verify_len); - return false; - } - - NET_INFO("Verification data:"); - print_buffer(verify, verify_len); - - NET_INFO("Result data:"); - print_buffer(result, result_len); - - if (memcmp(result, verify, result_len)) { - return false; - } - - return true; -} - -static bool ds_test(struct device *dev) -{ - u8_t key[] = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf }; - - u8_t auth_nonce[] = { 0xac, 0xde, 0x48, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x05, 0x02 }; - - u8_t auth_data[] = { 0x08, 0xd0, 0x84, 0x21, 0x43, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0x02, - 0x05, 0x00, 0x00, 0x00, 0x55, 0xcf, 0x00, - 0x00, 0x51, 0x52, 0x53, 0x54 }; - u8_t auth_result[] = { 0x08, 0xd0, 0x84, 0x21, 0x43, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0x02, - 0x05, 0x00, 0x00, 0x00, 0x55, 0xcf, 0x00, - 0x00, 0x51, 0x52, 0x53, 0x54, 0xca, 0x45, - 0x91, 0x8d, 0x3d, 0x82, 0xe5, 0xd0}; - u8_t enc_dec_nonce[] = { 0xac, 0xde, 0x48, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x05, 0x04 }; - u8_t enc_dec_data[] = { 0x69, 0xdc, 0x84, 0x21, 0x43, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, - 0x04, 0x05, 0x00, 0x00, 0x00, 0x61, 0x62, - 0x63, 0x64 }; - u8_t enc_dec_result[] = { 0x69, 0xdc, 0x84, 0x21, 0x43, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, - 0x04, 0x05, 0x00, 0x00, 0x00, 0x7c, 0x64, - 0xc5, 0x0a }; - u8_t both_op_nonce[] = { 0xac, 0xde, 0x48, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x05, 0x06 }; - u8_t both_op_data[] = { 0x2b, 0xdc, 0x84, 0x21, 0x43, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0xff, - 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x48, - 0xde, 0xac, 0x06, 0x05, 0x00, 0x00, 0x00, - 0x01, 0xce }; - u8_t both_op_result[] = { 0x2b, 0xdc, 0x84, 0x21, 0x43, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x48, 0xde, 0xac, 0xff, - 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x48, - 0xde, 0xac, 0x06, 0x05, 0x00, 0x00, 0x00, - 0x01, 0x2a, 0xaa, 0x80, 0xf2, 0x90, 0xb5, - 0xa3, 0xb6, 0xfe }; - int ret; - - /* Install the key */ - enc.key.bit_stream = key; - enc.keylen = sizeof(key); - dec.key.bit_stream = key; - dec.keylen = sizeof(key); - - /* Setup CCM parameters */ - enc.mode_params.ccm_info.nonce_len = 13U; - dec.mode_params.ccm_info.nonce_len = 13U; - - enc.flags = CAP_RAW_KEY | CAP_INPLACE_OPS | CAP_SYNC_OPS; - dec.flags = CAP_RAW_KEY | CAP_INPLACE_OPS | CAP_SYNC_OPS; - - apkt.pkt = &pkt; - - ret = cipher_begin_session(dev, &enc, - CRYPTO_CIPHER_ALGO_AES, - CRYPTO_CIPHER_MODE_CCM, - CRYPTO_CIPHER_OP_ENCRYPT); - if (ret) { - NET_ERR("Cannot start encryption session"); - return false; - } - - ret = cipher_begin_session(dev, &dec, - CRYPTO_CIPHER_ALGO_AES, - CRYPTO_CIPHER_MODE_CCM, - CRYPTO_CIPHER_OP_DECRYPT); - if (ret) { - NET_ERR("Cannot start decryption session"); - goto out; - } - - /* auth_data test: Authentify the packet only */ - memcpy(buf, auth_data, sizeof(auth_data)); - pkt.in_buf = NULL; - pkt.in_len = 0; - pkt.out_buf = buf; - pkt.out_buf_max = sizeof(buf); - - apkt.ad = buf; - apkt.ad_len = sizeof(auth_data); - - enc.mode_params.ccm_info.tag_len = 8U; - pkt.ctx = &enc; - - ret = cipher_ccm_op(&enc, &apkt, auth_nonce); - if (ret) { - NET_ERR("Cannot set authentication!"); - goto enc; - } - - if (!verify_result(buf, pkt.out_len, - auth_result, sizeof(auth_result))) { - NET_ERR("Authentication setting ds test failed!"); - goto enc; - } - - dec.mode_params.ccm_info.tag_len = 8U; - pkt.ctx = &dec; - - ret = cipher_ccm_op(&dec, &apkt, auth_nonce); - if (ret) { - NET_ERR("Cannot authentify!"); - goto enc; - } - - NET_INFO("Authentication only test: PASSED"); - -enc: - /* enc_dec_data test: Encrypt the packet only */ - memcpy(buf, enc_dec_data, sizeof(enc_dec_data)); - pkt.in_buf = buf + 26; - pkt.in_len = 4; - pkt.out_buf = buf; - pkt.out_buf_max = sizeof(buf); - - apkt.ad = buf; - apkt.ad_len = sizeof(enc_dec_data) - 4; - apkt.tag = NULL; - - /* No tag = no MIC, thus no auth */ - enc.mode_params.ccm_info.tag_len = 0U; - pkt.ctx = &enc; - - ret = cipher_ccm_op(&enc, &apkt, enc_dec_nonce); - if (ret) { - NET_ERR("Cannot encrypt only!"); - goto out; - } - - if (!verify_result(buf, pkt.out_len, - enc_dec_result, sizeof(enc_dec_result))) { - NET_ERR("Encryption only ds test failed!"); - goto both; - } - - dec.mode_params.ccm_info.tag_len = 0U; - pkt.ctx = &dec; - - ret = cipher_ccm_op(&dec, &apkt, enc_dec_nonce); - if (ret) { - NET_ERR("Cannot decrypt only!"); - goto both; - } - - if (!verify_result(buf, pkt.out_len, - enc_dec_data, sizeof(enc_dec_data))) { - NET_ERR("Decryption only ds test failed!"); - } - - NET_INFO("Encryption only test: PASSED"); - -both: - /* both_op_data test: Both auth+encryption */ - memcpy(buf, both_op_data, sizeof(both_op_data)); - pkt.in_buf = buf + 29; - pkt.in_len = 1; - pkt.out_buf = buf; - pkt.out_buf_max = sizeof(buf); - - apkt.ad = buf; - apkt.ad_len = sizeof(both_op_data) - 1; - apkt.tag = NULL; - - enc.mode_params.ccm_info.tag_len = 8U; - pkt.ctx = &enc; - - ret = cipher_ccm_op(&enc, &apkt, both_op_nonce); - if (ret) { - NET_ERR("Cannot do both!"); - goto out; - } - - if (!verify_result(buf, pkt.out_len, - both_op_result, sizeof(both_op_result))) { - NET_ERR("Both op test failed!"); - goto out; - } - - pkt.in_len = 1 + 8; - dec.mode_params.ccm_info.tag_len = 8U; - pkt.ctx = &dec; - - ret = cipher_ccm_op(&dec, &apkt, both_op_nonce); - if (ret) { - NET_ERR("Cannot do both!"); - goto out; - } - - if (!verify_result(buf, pkt.out_len - dec.mode_params.ccm_info.tag_len, - both_op_data, sizeof(both_op_data))) { - NET_ERR("Both op test failed!"); - } - - NET_INFO("Authentication and encryption test: PASSED"); - - return true; -out: - cipher_free_session(dev, &enc); - cipher_free_session(dev, &dec); - - return false; -} - -static void test_cc2520_crypto(void) -{ - struct device *dev; - - dev = device_get_binding(IEEE802154_CRYPTO_DRV_NAME); - zassert_not_null(dev, NULL); - - print_caps(dev); - - zassert_true(ds_test(dev), NULL); -} - - -void test_main(void) -{ - ztest_test_suite(ieee802154_crypto, - ztest_unit_test(test_cc2520_crypto) - ); - - ztest_run_test_suite(ieee802154_crypto); -} diff --git a/tests/net/ieee802154/crypto/testcase.yaml b/tests/net/ieee802154/crypto/testcase.yaml deleted file mode 100644 index 1e40ae0dbe5..00000000000 --- a/tests/net/ieee802154/crypto/testcase.yaml +++ /dev/null @@ -1,13 +0,0 @@ -common: - depends_on: ieee802154 - platform_whitelist: quark_se_c1000_devboard -tests: - net.ieee802154.crypto: - tags: net crypto - harness: console - harness_config: - type: multi_line - regex: - - ".*ds_test: Authentication only test: PASSED" - - ".*ds_test: Encryption only test: PASSED" - - ".*Authentication and encryption test: PASSED"