diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c
index 0130bdd5a1f..7fdcfec332c 100644
--- a/arch/arm/core/aarch32/irq_manage.c
+++ b/arch/arm/core/aarch32/irq_manage.c
@@ -88,10 +88,10 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 	 * affecting performance (can still be useful on systems with a
 	 * reduced set of priorities, like Cortex-M0/M0+).
 	 */
-	__ASSERT(prio <= (BIT(DT_NUM_IRQ_PRIO_BITS) - 1),
+	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
 		 "invalid priority %d! values must be less than %lu\n",
 		 prio - _IRQ_PRIO_OFFSET,
-		 BIT(DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
+		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
 
diff --git a/include/arch/arm/aarch32/cortex_m/cmsis.h b/include/arch/arm/aarch32/cortex_m/cmsis.h
index ea15511088c..1e6e2513501 100644
--- a/include/arch/arm/aarch32/cortex_m/cmsis.h
+++ b/include/arch/arm/aarch32/cortex_m/cmsis.h
@@ -16,10 +16,13 @@
 
 #include <soc.h>
 
+#include <arch/arm/aarch32/cortex_m/nvic.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+
 /* CP10 Access Bits */
 #define CPACR_CP10_Pos          20U
 #define CPACR_CP10_Msk          (3UL << CPACR_CP10_Pos)
@@ -84,12 +87,12 @@ typedef enum {
 #ifndef __MPU_PRESENT
 #define __MPU_PRESENT             0U
 #endif
-#define __NVIC_PRIO_BITS               DT_NUM_IRQ_PRIO_BITS
+#define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
 #define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
 #endif /* __NVIC_PRIO_BITS */
 
-#if __NVIC_PRIO_BITS != DT_NUM_IRQ_PRIO_BITS
-#error "DT_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
+#if __NVIC_PRIO_BITS != NUM_IRQ_PRIO_BITS
+#error "NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
 #endif
 
 #ifdef __cplusplus
diff --git a/include/arch/arm/aarch32/cortex_m/nvic.h b/include/arch/arm/aarch32/cortex_m/nvic.h
new file mode 100644
index 00000000000..9bb8bee7856
--- /dev/null
+++ b/include/arch/arm/aarch32/cortex_m/nvic.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
+
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+/* The order here is on purpose since ARMv8-M SoCs may define
+ * CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE
+ * so we want to check for ARMv8-M first.
+ */
+#define NVIC_NODEID DT_INST(0, arm_v8m_nvic)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+#define NVIC_NODEID DT_INST(0, arm_v7m_nvic)
+#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+#define NVIC_NODEID DT_INST(0, arm_v6m_nvic)
+#endif
+
+#define NUM_IRQ_PRIO_BITS DT_PROP(NVIC_NODEID, arm_num_irq_priority_bits)
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_ */
diff --git a/include/arch/arm/aarch32/exc.h b/include/arch/arm/aarch32/exc.h
index 729afba37c7..423135fee3e 100644
--- a/include/arch/arm/aarch32/exc.h
+++ b/include/arch/arm/aarch32/exc.h
@@ -17,8 +17,10 @@
 
 #include <devicetree.h>
 
+#include <arch/arm/aarch32/cortex_m/nvic.h>
+
 /* for assembler, only works with constants */
-#define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
+#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
 
 /*
  * In architecture variants with non-programmable fault exceptions
diff --git a/soc/arm/bcm_vk/valkyrie/soc.h b/soc/arm/bcm_vk/valkyrie/soc.h
index b3127405eae..adc905339a3 100644
--- a/soc/arm/bcm_vk/valkyrie/soc.h
+++ b/soc/arm/bcm_vk/valkyrie/soc.h
@@ -280,6 +280,6 @@ typedef enum IRQn {
  */
 
 #define __MPU_PRESENT           1
-#define __NVIC_PRIO_BITS        DT_NUM_IRQ_PRIO_BITS
+#define __NVIC_PRIO_BITS        NUM_IRQ_PRIO_BITS
 
 #endif
diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h b/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h
index ca4d388c85f..a1d3504b986 100644
--- a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h
+++ b/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h
@@ -23,7 +23,7 @@ typedef enum {
 
 #define __CM4_REV              0
 #define __MPU_PRESENT          1
-#define __NVIC_PRIO_BITS       DT_NUM_IRQ_PRIO_BITS
+#define __NVIC_PRIO_BITS       NUM_IRQ_PRIO_BITS
 #define __Vendor_SysTickConfig 0
 #define __FPU_PRESENT          1
 
diff --git a/soc/arm/ti_simplelink/cc32xx/soc.h b/soc/arm/ti_simplelink/cc32xx/soc.h
index 7b0d752c656..1300b70e48c 100644
--- a/soc/arm/ti_simplelink/cc32xx/soc.h
+++ b/soc/arm/ti_simplelink/cc32xx/soc.h
@@ -35,7 +35,7 @@ typedef enum {
 
 #define __CM4_REV        0
 #define __MPU_PRESENT                  0 /* Zephyr has no MPU support */
-#define __NVIC_PRIO_BITS               DT_NUM_IRQ_PRIO_BITS
+#define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
 #define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
 
 #endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */