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kernel: abolish _default_esf

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NANO_ESF parameters may now be NULL, indicating that no
exception frame is available.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-07-15 15:22:29 -07:00 • committed by Andrew Boie
commit 5623637a48
17 changed files with 58 additions and 141 deletions
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59
arch/nios2/core/fatal.c
View file

@ -11,48 +11,29 @@
#include <inttypes.h> #include <inttypes.h>
#include <logging/log_ctrl.h> #include <logging/log_ctrl.h>
const NANO_ESF _default_esf = {
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad
};
FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason,
const NANO_ESF *esf) const NANO_ESF *esf)
{ {
/* Subtract 4 from EA since we added 4 earlier so that the faulting if (esf != NULL) {
* instruction isn't retried. /* Subtract 4 from EA since we added 4 earlier so that the
* * faulting instruction isn't retried.
* TODO: Only caller-saved registers get saved upon exception entry. *
* We may want to introduce a config option to save and dump all * TODO: Only caller-saved registers get saved upon exception
* registers, at the expense of some stack space. * entry. We may want to introduce a config option to save and
*/ * dump all registers, at the expense of some stack space.
printk("Faulting instruction: 0x%x\n" */
" r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n" printk("Faulting instruction: 0x%x\n"
" r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n" " r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n"
" r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n" " r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n"
" r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n" " r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n"
"estatus: %x\n", esf->instr - 4, " r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n"
esf->r1, esf->r2, esf->r3, esf->r4, "estatus: %x\n", esf->instr - 4,
esf->r5, esf->r6, esf->r7, esf->r8, esf->r1, esf->r2, esf->r3, esf->r4,
esf->r9, esf->r10, esf->r11, esf->r12, esf->r5, esf->r6, esf->r7, esf->r8,
esf->r13, esf->r14, esf->r15, esf->ra, esf->r9, esf->r10, esf->r11, esf->r12,
esf->estatus); esf->r13, esf->r14, esf->r15, esf->ra,
esf->estatus);
}
z_fatal_error(reason, esf); z_fatal_error(reason, esf);
CODE_UNREACHABLE; CODE_UNREACHABLE;

2
arch/nios2/core/irq_manage.c
View file

@ -26,7 +26,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused)
ARG_UNUSED(unused); ARG_UNUSED(unused);
printk("Spurious interrupt detected! ipending: %x\n", printk("Spurious interrupt detected! ipending: %x\n",
z_nios2_creg_read(NIOS2_CR_IPENDING)); z_nios2_creg_read(NIOS2_CR_IPENDING));
z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }

4
arch/posix/core/fatal.c
View file

@ -13,10 +13,6 @@
#include <logging/log_ctrl.h> #include <logging/log_ctrl.h>
#include "posix_soc_if.h" #include "posix_soc_if.h"
const NANO_ESF _default_esf = {
0xdeadbaad
};
FUNC_NORETURN void z_arch_system_halt(unsigned int reason) FUNC_NORETURN void z_arch_system_halt(unsigned int reason)
{ {
ARG_UNUSED(reason); ARG_UNUSED(reason);

54
arch/riscv32/core/fatal.c
View file

@ -10,49 +10,23 @@
#include <sys/printk.h> #include <sys/printk.h>
#include <logging/log_ctrl.h> #include <logging/log_ctrl.h>
const NANO_ESF _default_esf = {
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
0xdeadbaad,
#if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE)
{
SOC_ESF_INIT,
},
#endif
};
FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason, FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason,
const NANO_ESF *esf) const NANO_ESF *esf)
{ {
printk("Faulting instruction address = 0x%x\n" if (esf != NULL) {
" ra: 0x%x gp: 0x%x tp: 0x%x t0: 0x%x\n" printk("Faulting instruction address = 0x%x\n"
" t1: 0x%x t2: 0x%x t3: 0x%x t4: 0x%x\n" " ra: 0x%x gp: 0x%x tp: 0x%x t0: 0x%x\n"
" t5: 0x%x t6: 0x%x a0: 0x%x a1: 0x%x\n" " t1: 0x%x t2: 0x%x t3: 0x%x t4: 0x%x\n"
" a2: 0x%x a3: 0x%x a4: 0x%x a5: 0x%x\n" " t5: 0x%x t6: 0x%x a0: 0x%x a1: 0x%x\n"
" a6: 0x%x a7: 0x%x\n", " a2: 0x%x a3: 0x%x a4: 0x%x a5: 0x%x\n"
(esf->mepc == 0xdeadbaad) ? 0xdeadbaad : esf->mepc, " a6: 0x%x a7: 0x%x\n",
esf->ra, esf->gp, esf->tp, esf->t0, esf->mepc,
esf->t1, esf->t2, esf->t3, esf->t4, esf->ra, esf->gp, esf->tp, esf->t0,
esf->t5, esf->t6, esf->a0, esf->a1, esf->t1, esf->t2, esf->t3, esf->t4,
esf->a2, esf->a3, esf->a4, esf->a5, esf->t5, esf->t6, esf->a0, esf->a1,
esf->a6, esf->a7); esf->a2, esf->a3, esf->a4, esf->a5,
esf->a6, esf->a7);
}
z_fatal_error(reason, esf); z_fatal_error(reason, esf);
CODE_UNREACHABLE; CODE_UNREACHABLE;

2
arch/riscv32/core/irq_manage.c
View file

@ -25,7 +25,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused)
riscv_plic_get_irq()); riscv_plic_get_irq());
} }
#endif #endif
z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
#ifdef CONFIG_DYNAMIC_INTERRUPTS #ifdef CONFIG_DYNAMIC_INTERRUPTS

39
arch/x86/core/ia32/fatal.c
View file

@ -131,19 +131,21 @@ FUNC_NORETURN void z_arch_system_halt(unsigned int reason)
FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, const NANO_ESF *esf) FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, const NANO_ESF *esf)
{ {
printk("eax: 0x%08x, ebx: 0x%08x, ecx: 0x%08x, edx: 0x%08x\n" if (esf != NULL) {
"esi: 0x%08x, edi: 0x%08x, ebp: 0x%08x, esp: 0x%08x\n" printk("eax: 0x%08x, ebx: 0x%08x, ecx: 0x%08x, edx: 0x%08x\n"
"eflags: 0x%08x cs: 0x%04x\n" "esi: 0x%08x, edi: 0x%08x, ebp: 0x%08x, esp: 0x%08x\n"
"eflags: 0x%08x cs: 0x%04x\n"
#ifdef CONFIG_EXCEPTION_STACK_TRACE #ifdef CONFIG_EXCEPTION_STACK_TRACE
"call trace:\n" "call trace:\n"
#endif #endif
"eip: 0x%08x\n", "eip: 0x%08x\n",
esf->eax, esf->ebx, esf->ecx, esf->edx, esf->eax, esf->ebx, esf->ecx, esf->edx,
esf->esi, esf->edi, esf->ebp, esf->esp, esf->esi, esf->edi, esf->ebp, esf->esp,
esf->eflags, esf->cs & 0xFFFFU, esf->eip); esf->eflags, esf->cs & 0xFFFFU, esf->eip);
#ifdef CONFIG_EXCEPTION_STACK_TRACE #ifdef CONFIG_EXCEPTION_STACK_TRACE
unwind_stack(esf->ebp, esf->cs); unwind_stack(esf->ebp, esf->cs);
#endif #endif
}
z_fatal_error(reason, esf); z_fatal_error(reason, esf);
CODE_UNREACHABLE; CODE_UNREACHABLE;
@ -202,25 +204,6 @@ NANO_CPU_INT_REGISTER(_kernel_oops_handler, NANO_SOFT_IRQ,
CONFIG_X86_KERNEL_OOPS_VECTOR, 3); CONFIG_X86_KERNEL_OOPS_VECTOR, 3);
#endif #endif
/*
* Define a default ESF for use with z_fatal_error() in the event
* the caller does not have a NANO_ESF to pass
*/
const NANO_ESF _default_esf = {
0xdeaddead, /* ESP */
0xdeaddead, /* EBP */
0xdeaddead, /* EBX */
0xdeaddead, /* ESI */
0xdeaddead, /* EDI */
0xdeaddead, /* EDX */
0xdeaddead, /* ECX */
0xdeaddead, /* EAX */
0xdeaddead, /* error code */
0xdeaddead, /* EIP */
0xdeaddead, /* CS */
0xdeaddead, /* EFLAGS */
};
#if CONFIG_EXCEPTION_DEBUG #if CONFIG_EXCEPTION_DEBUG
FUNC_NORETURN static void generic_exc_handle(unsigned int vector, FUNC_NORETURN static void generic_exc_handle(unsigned int vector,

3
arch/x86_64/core/x86_64.c
View file

@ -59,6 +59,7 @@ void z_unhandled_vector(int vector, int err, struct xuk_entry_frame *f)
printk("*** R8 0x%llx R9 0x%llx R10 0x%llx R11 0x%llx\n", printk("*** R8 0x%llx R9 0x%llx R10 0x%llx R11 0x%llx\n",
f->r8, f->r9, f->r10, f->r11); f->r8, f->r9, f->r10, f->r11);
/* FIXME: Why isn't xuk_entry_frame a NANO_ESF? */
z_fatal_error(x86_64_except_reason, NULL); z_fatal_error(x86_64_except_reason, NULL);
} }
@ -211,6 +212,4 @@ void x86_apic_set_timeout(u32_t cyc_from_now)
_apic.INIT_COUNT = cyc_from_now; _apic.INIT_COUNT = cyc_from_now;
} }
const NANO_ESF _default_esf;
int x86_64_except_reason; int x86_64_except_reason;

13
arch/xtensa/core/fatal.c
View file

@ -16,11 +16,6 @@
#include <xtensa/simcall.h> #include <xtensa/simcall.h>
#endif #endif
const NANO_ESF _default_esf = {
{0xdeaddead}, /* sp */
0xdeaddead, /* pc */
};
/* Need to do this as a macro since regnum must be an immediate value */ /* Need to do this as a macro since regnum must be an immediate value */
#define get_sreg(regnum_p) ({ \ #define get_sreg(regnum_p) ({ \
unsigned int retval; \ unsigned int retval; \
@ -126,14 +121,16 @@ XTENSA_ERR_NORET void z_xtensa_fatal_error(unsigned int reason,
{ {
dump_exc_state(); dump_exc_state();
printk("Faulting instruction address = 0x%x\n", esf->pc); if (esf) {
printk("Faulting instruction address = 0x%x\n", esf->pc);
}
z_fatal_error(reason, esf); z_fatal_error(reason, esf);
} }
XTENSA_ERR_NORET void FatalErrorHandler(void) XTENSA_ERR_NORET void FatalErrorHandler(void)
{ {
z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, &_default_esf); z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, NULL);
} }
XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo) XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo)
@ -141,7 +138,7 @@ XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo)
printk("INTENABLE = 0x%x\n" printk("INTENABLE = 0x%x\n"
"INTERRUPT = 0x%x (%x)\n", "INTERRUPT = 0x%x (%x)\n",
get_sreg(INTENABLE), (1 << intNo), intNo); get_sreg(INTENABLE), (1 << intNo), intNo);
z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
void exit(int return_code) void exit(int return_code)

6
arch/xtensa/core/xtensa-asm2.c
View file

@ -87,7 +87,7 @@ void z_irq_spurious(void *arg)
__asm__ volatile("rsr.intenable %0" : "=r"(ie)); __asm__ volatile("rsr.intenable %0" : "=r"(ie));
printk(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p\n", printk(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p\n",
(void *)irqs, (void *)ie); (void *)irqs, (void *)ie);
z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
#endif #endif
@ -200,8 +200,10 @@ void *xtensa_excint1_c(int *interrupted_stack)
* for all unhandled exceptions, which seems incorrect * for all unhandled exceptions, which seems incorrect
* as these are software errors. Should clean this * as these are software errors. Should clean this
* up. * up.
*
* FIXME: interrupted_stack and NANO_ESF ought to be the same
*/ */
z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, &_default_esf); z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, NULL);
} }
return z_get_next_switch_handle(interrupted_stack); return z_get_next_switch_handle(interrupted_stack);

1
include/arch/nios2/arch.h
View file

@ -151,7 +151,6 @@ struct __esf {
}; };
typedef struct __esf NANO_ESF; typedef struct __esf NANO_ESF;
extern const NANO_ESF _default_esf;
FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason, FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason,
const NANO_ESF *esf); const NANO_ESF *esf);

1
include/arch/posix/arch.h
View file

@ -38,7 +38,6 @@ struct __esf {
}; };
typedef struct __esf NANO_ESF; typedef struct __esf NANO_ESF;
extern const NANO_ESF _default_esf;
extern u32_t z_timer_cycle_get_32(void); extern u32_t z_timer_cycle_get_32(void);
#define z_arch_k_cycle_get_32() z_timer_cycle_get_32() #define z_arch_k_cycle_get_32() z_timer_cycle_get_32()

1
include/arch/riscv32/exp.h
View file

@ -75,7 +75,6 @@ typedef struct __esf NANO_ESF;
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
typedef struct soc_esf soc_esf_t; typedef struct soc_esf soc_esf_t;
#endif #endif
extern const NANO_ESF _default_esf;
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#ifdef __cplusplus #ifdef __cplusplus

3
include/arch/x86/ia32/arch.h
View file

@ -655,9 +655,6 @@ extern struct task_state_segment _main_tss;
} while (false) } while (false)
#endif #endif
/** Dummy ESF for fatal errors that would otherwise not have an ESF */
extern const NANO_ESF _default_esf;
#ifdef CONFIG_X86_MMU #ifdef CONFIG_X86_MMU
/* kernel's page table */ /* kernel's page table */
extern struct x86_mmu_pdpt z_x86_kernel_pdpt; extern struct x86_mmu_pdpt z_x86_kernel_pdpt;

1
include/arch/x86_64/arch.h
View file

@ -13,5 +13,4 @@
#define STACK_ALIGN 8 #define STACK_ALIGN 8
typedef struct NANO_ESF NANO_ESF; typedef struct NANO_ESF NANO_ESF;
extern const NANO_ESF _default_esf;
#endif /* _X86_64_ARCH_H */ #endif /* _X86_64_ARCH_H */

1
include/arch/xtensa/exc.h
View file

@ -33,7 +33,6 @@ struct __esf {
}; };
typedef struct __esf NANO_ESF; typedef struct __esf NANO_ESF;
extern const NANO_ESF _default_esf;
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

7
include/fatal.h
View file

@ -9,13 +9,6 @@
#include <arch/cpu.h> #include <arch/cpu.h>
/* TODO Items:
*
* - Delete default_esf everywhere, just pass a NULL pointer around in that
* situation
*
*/
enum k_fatal_error_reason { enum k_fatal_error_reason {
/** Generic CPU exception, not covered by other codes */ /** Generic CPU exception, not covered by other codes */
K_ERR_CPU_EXCEPTION, K_ERR_CPU_EXCEPTION,

2
include/kernel.h
View file

@ -4658,7 +4658,7 @@ extern void z_sys_power_save_idle_exit(s32_t ticks);
*/ */
#define z_except_reason(reason) do { \ #define z_except_reason(reason) do { \
printk("@ %s:%d:\n", __FILE__, __LINE__); \ printk("@ %s:%d:\n", __FILE__, __LINE__); \
z_fatal_error(reason, &_default_esf); \ z_fatal_error(reason, NULL); \
} while (false) } while (false)
#endif /* _ARCH__EXCEPT */ #endif /* _ARCH__EXCEPT */