From 5623637a484be363a20af23ea499ba53ce87fd23 Mon Sep 17 00:00:00 2001 From: Andrew Boie Date: Mon, 15 Jul 2019 15:22:29 -0700 Subject: [PATCH] kernel: abolish _default_esf NANO_ESF parameters may now be NULL, indicating that no exception frame is available. Signed-off-by: Andrew Boie --- arch/nios2/core/fatal.c | 59 ++++++++++++---------------------- arch/nios2/core/irq_manage.c | 2 +- arch/posix/core/fatal.c | 4 --- arch/riscv32/core/fatal.c | 54 ++++++++----------------------- arch/riscv32/core/irq_manage.c | 2 +- arch/x86/core/ia32/fatal.c | 39 +++++++--------------- arch/x86_64/core/x86_64.c | 3 +- arch/xtensa/core/fatal.c | 13 +++----- arch/xtensa/core/xtensa-asm2.c | 6 ++-- include/arch/nios2/arch.h | 1 - include/arch/posix/arch.h | 1 - include/arch/riscv32/exp.h | 1 - include/arch/x86/ia32/arch.h | 3 -- include/arch/x86_64/arch.h | 1 - include/arch/xtensa/exc.h | 1 - include/fatal.h | 7 ---- include/kernel.h | 2 +- 17 files changed, 58 insertions(+), 141 deletions(-) diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c index bb1314d624a..1fce61ae429 100644 --- a/arch/nios2/core/fatal.c +++ b/arch/nios2/core/fatal.c @@ -11,48 +11,29 @@ #include #include -const NANO_ESF _default_esf = { - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad -}; - FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, const NANO_ESF *esf) { - /* Subtract 4 from EA since we added 4 earlier so that the faulting - * instruction isn't retried. - * - * TODO: Only caller-saved registers get saved upon exception entry. - * We may want to introduce a config option to save and dump all - * registers, at the expense of some stack space. - */ - printk("Faulting instruction: 0x%x\n" - " r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n" - " r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n" - " r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n" - " r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n" - "estatus: %x\n", esf->instr - 4, - esf->r1, esf->r2, esf->r3, esf->r4, - esf->r5, esf->r6, esf->r7, esf->r8, - esf->r9, esf->r10, esf->r11, esf->r12, - esf->r13, esf->r14, esf->r15, esf->ra, - esf->estatus); + if (esf != NULL) { + /* Subtract 4 from EA since we added 4 earlier so that the + * faulting instruction isn't retried. + * + * TODO: Only caller-saved registers get saved upon exception + * entry. We may want to introduce a config option to save and + * dump all registers, at the expense of some stack space. + */ + printk("Faulting instruction: 0x%x\n" + " r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n" + " r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n" + " r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n" + " r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n" + "estatus: %x\n", esf->instr - 4, + esf->r1, esf->r2, esf->r3, esf->r4, + esf->r5, esf->r6, esf->r7, esf->r8, + esf->r9, esf->r10, esf->r11, esf->r12, + esf->r13, esf->r14, esf->r15, esf->ra, + esf->estatus); + } z_fatal_error(reason, esf); CODE_UNREACHABLE; diff --git a/arch/nios2/core/irq_manage.c b/arch/nios2/core/irq_manage.c index c90b7cdc2ac..b91de9d7461 100644 --- a/arch/nios2/core/irq_manage.c +++ b/arch/nios2/core/irq_manage.c @@ -26,7 +26,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused) ARG_UNUSED(unused); printk("Spurious interrupt detected! ipending: %x\n", z_nios2_creg_read(NIOS2_CR_IPENDING)); - z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); + z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } diff --git a/arch/posix/core/fatal.c b/arch/posix/core/fatal.c index c5b05b1ba17..d5e09660f1a 100644 --- a/arch/posix/core/fatal.c +++ b/arch/posix/core/fatal.c @@ -13,10 +13,6 @@ #include #include "posix_soc_if.h" -const NANO_ESF _default_esf = { - 0xdeadbaad -}; - FUNC_NORETURN void z_arch_system_halt(unsigned int reason) { ARG_UNUSED(reason); diff --git a/arch/riscv32/core/fatal.c b/arch/riscv32/core/fatal.c index a1a4a30ad15..0531721a030 100644 --- a/arch/riscv32/core/fatal.c +++ b/arch/riscv32/core/fatal.c @@ -10,49 +10,23 @@ #include #include -const NANO_ESF _default_esf = { - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, - 0xdeadbaad, -#if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE) - { - SOC_ESF_INIT, - }, -#endif -}; - FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason, const NANO_ESF *esf) { - printk("Faulting instruction address = 0x%x\n" - " ra: 0x%x gp: 0x%x tp: 0x%x t0: 0x%x\n" - " t1: 0x%x t2: 0x%x t3: 0x%x t4: 0x%x\n" - " t5: 0x%x t6: 0x%x a0: 0x%x a1: 0x%x\n" - " a2: 0x%x a3: 0x%x a4: 0x%x a5: 0x%x\n" - " a6: 0x%x a7: 0x%x\n", - (esf->mepc == 0xdeadbaad) ? 0xdeadbaad : esf->mepc, - esf->ra, esf->gp, esf->tp, esf->t0, - esf->t1, esf->t2, esf->t3, esf->t4, - esf->t5, esf->t6, esf->a0, esf->a1, - esf->a2, esf->a3, esf->a4, esf->a5, - esf->a6, esf->a7); + if (esf != NULL) { + printk("Faulting instruction address = 0x%x\n" + " ra: 0x%x gp: 0x%x tp: 0x%x t0: 0x%x\n" + " t1: 0x%x t2: 0x%x t3: 0x%x t4: 0x%x\n" + " t5: 0x%x t6: 0x%x a0: 0x%x a1: 0x%x\n" + " a2: 0x%x a3: 0x%x a4: 0x%x a5: 0x%x\n" + " a6: 0x%x a7: 0x%x\n", + esf->mepc, + esf->ra, esf->gp, esf->tp, esf->t0, + esf->t1, esf->t2, esf->t3, esf->t4, + esf->t5, esf->t6, esf->a0, esf->a1, + esf->a2, esf->a3, esf->a4, esf->a5, + esf->a6, esf->a7); + } z_fatal_error(reason, esf); CODE_UNREACHABLE; diff --git a/arch/riscv32/core/irq_manage.c b/arch/riscv32/core/irq_manage.c index b10cd985b53..875c80b3c25 100644 --- a/arch/riscv32/core/irq_manage.c +++ b/arch/riscv32/core/irq_manage.c @@ -25,7 +25,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused) riscv_plic_get_irq()); } #endif - z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); + z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } #ifdef CONFIG_DYNAMIC_INTERRUPTS diff --git a/arch/x86/core/ia32/fatal.c b/arch/x86/core/ia32/fatal.c index db8010400fc..68fb48c2160 100644 --- a/arch/x86/core/ia32/fatal.c +++ b/arch/x86/core/ia32/fatal.c @@ -131,19 +131,21 @@ FUNC_NORETURN void z_arch_system_halt(unsigned int reason) FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, const NANO_ESF *esf) { - printk("eax: 0x%08x, ebx: 0x%08x, ecx: 0x%08x, edx: 0x%08x\n" - "esi: 0x%08x, edi: 0x%08x, ebp: 0x%08x, esp: 0x%08x\n" - "eflags: 0x%08x cs: 0x%04x\n" + if (esf != NULL) { + printk("eax: 0x%08x, ebx: 0x%08x, ecx: 0x%08x, edx: 0x%08x\n" + "esi: 0x%08x, edi: 0x%08x, ebp: 0x%08x, esp: 0x%08x\n" + "eflags: 0x%08x cs: 0x%04x\n" #ifdef CONFIG_EXCEPTION_STACK_TRACE - "call trace:\n" + "call trace:\n" #endif - "eip: 0x%08x\n", - esf->eax, esf->ebx, esf->ecx, esf->edx, - esf->esi, esf->edi, esf->ebp, esf->esp, - esf->eflags, esf->cs & 0xFFFFU, esf->eip); + "eip: 0x%08x\n", + esf->eax, esf->ebx, esf->ecx, esf->edx, + esf->esi, esf->edi, esf->ebp, esf->esp, + esf->eflags, esf->cs & 0xFFFFU, esf->eip); #ifdef CONFIG_EXCEPTION_STACK_TRACE - unwind_stack(esf->ebp, esf->cs); + unwind_stack(esf->ebp, esf->cs); #endif + } z_fatal_error(reason, esf); CODE_UNREACHABLE; @@ -202,25 +204,6 @@ NANO_CPU_INT_REGISTER(_kernel_oops_handler, NANO_SOFT_IRQ, CONFIG_X86_KERNEL_OOPS_VECTOR, 3); #endif -/* - * Define a default ESF for use with z_fatal_error() in the event - * the caller does not have a NANO_ESF to pass - */ -const NANO_ESF _default_esf = { - 0xdeaddead, /* ESP */ - 0xdeaddead, /* EBP */ - 0xdeaddead, /* EBX */ - 0xdeaddead, /* ESI */ - 0xdeaddead, /* EDI */ - 0xdeaddead, /* EDX */ - 0xdeaddead, /* ECX */ - 0xdeaddead, /* EAX */ - 0xdeaddead, /* error code */ - 0xdeaddead, /* EIP */ - 0xdeaddead, /* CS */ - 0xdeaddead, /* EFLAGS */ -}; - #if CONFIG_EXCEPTION_DEBUG FUNC_NORETURN static void generic_exc_handle(unsigned int vector, diff --git a/arch/x86_64/core/x86_64.c b/arch/x86_64/core/x86_64.c index 93bbe646e30..537f7ad6c89 100644 --- a/arch/x86_64/core/x86_64.c +++ b/arch/x86_64/core/x86_64.c @@ -59,6 +59,7 @@ void z_unhandled_vector(int vector, int err, struct xuk_entry_frame *f) printk("*** R8 0x%llx R9 0x%llx R10 0x%llx R11 0x%llx\n", f->r8, f->r9, f->r10, f->r11); + /* FIXME: Why isn't xuk_entry_frame a NANO_ESF? */ z_fatal_error(x86_64_except_reason, NULL); } @@ -211,6 +212,4 @@ void x86_apic_set_timeout(u32_t cyc_from_now) _apic.INIT_COUNT = cyc_from_now; } -const NANO_ESF _default_esf; - int x86_64_except_reason; diff --git a/arch/xtensa/core/fatal.c b/arch/xtensa/core/fatal.c index 59f9cf93523..03b3d601792 100644 --- a/arch/xtensa/core/fatal.c +++ b/arch/xtensa/core/fatal.c @@ -16,11 +16,6 @@ #include #endif -const NANO_ESF _default_esf = { - {0xdeaddead}, /* sp */ - 0xdeaddead, /* pc */ -}; - /* Need to do this as a macro since regnum must be an immediate value */ #define get_sreg(regnum_p) ({ \ unsigned int retval; \ @@ -126,14 +121,16 @@ XTENSA_ERR_NORET void z_xtensa_fatal_error(unsigned int reason, { dump_exc_state(); - printk("Faulting instruction address = 0x%x\n", esf->pc); + if (esf) { + printk("Faulting instruction address = 0x%x\n", esf->pc); + } z_fatal_error(reason, esf); } XTENSA_ERR_NORET void FatalErrorHandler(void) { - z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, &_default_esf); + z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, NULL); } XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo) @@ -141,7 +138,7 @@ XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo) printk("INTENABLE = 0x%x\n" "INTERRUPT = 0x%x (%x)\n", get_sreg(INTENABLE), (1 << intNo), intNo); - z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); + z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } void exit(int return_code) diff --git a/arch/xtensa/core/xtensa-asm2.c b/arch/xtensa/core/xtensa-asm2.c index 999af2321f1..6e235569185 100644 --- a/arch/xtensa/core/xtensa-asm2.c +++ b/arch/xtensa/core/xtensa-asm2.c @@ -87,7 +87,7 @@ void z_irq_spurious(void *arg) __asm__ volatile("rsr.intenable %0" : "=r"(ie)); printk(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p\n", (void *)irqs, (void *)ie); - z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, &_default_esf); + z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } #endif @@ -200,8 +200,10 @@ void *xtensa_excint1_c(int *interrupted_stack) * for all unhandled exceptions, which seems incorrect * as these are software errors. Should clean this * up. + * + * FIXME: interrupted_stack and NANO_ESF ought to be the same */ - z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, &_default_esf); + z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, NULL); } return z_get_next_switch_handle(interrupted_stack); diff --git a/include/arch/nios2/arch.h b/include/arch/nios2/arch.h index ce9a4d54c03..6221bf994d5 100644 --- a/include/arch/nios2/arch.h +++ b/include/arch/nios2/arch.h @@ -151,7 +151,6 @@ struct __esf { }; typedef struct __esf NANO_ESF; -extern const NANO_ESF _default_esf; FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf); diff --git a/include/arch/posix/arch.h b/include/arch/posix/arch.h index a436cf6e82d..7068018c918 100644 --- a/include/arch/posix/arch.h +++ b/include/arch/posix/arch.h @@ -38,7 +38,6 @@ struct __esf { }; typedef struct __esf NANO_ESF; -extern const NANO_ESF _default_esf; extern u32_t z_timer_cycle_get_32(void); #define z_arch_k_cycle_get_32() z_timer_cycle_get_32() diff --git a/include/arch/riscv32/exp.h b/include/arch/riscv32/exp.h index b716cc6a978..64070305f5c 100644 --- a/include/arch/riscv32/exp.h +++ b/include/arch/riscv32/exp.h @@ -75,7 +75,6 @@ typedef struct __esf NANO_ESF; #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE typedef struct soc_esf soc_esf_t; #endif -extern const NANO_ESF _default_esf; #endif /* _ASMLANGUAGE */ #ifdef __cplusplus diff --git a/include/arch/x86/ia32/arch.h b/include/arch/x86/ia32/arch.h index c3c23eed6b6..55236ee4505 100644 --- a/include/arch/x86/ia32/arch.h +++ b/include/arch/x86/ia32/arch.h @@ -655,9 +655,6 @@ extern struct task_state_segment _main_tss; } while (false) #endif -/** Dummy ESF for fatal errors that would otherwise not have an ESF */ -extern const NANO_ESF _default_esf; - #ifdef CONFIG_X86_MMU /* kernel's page table */ extern struct x86_mmu_pdpt z_x86_kernel_pdpt; diff --git a/include/arch/x86_64/arch.h b/include/arch/x86_64/arch.h index 73a88d78dbb..1eb7b79aca8 100644 --- a/include/arch/x86_64/arch.h +++ b/include/arch/x86_64/arch.h @@ -13,5 +13,4 @@ #define STACK_ALIGN 8 typedef struct NANO_ESF NANO_ESF; -extern const NANO_ESF _default_esf; #endif /* _X86_64_ARCH_H */ diff --git a/include/arch/xtensa/exc.h b/include/arch/xtensa/exc.h index bf9bff65981..e725e1d2b2d 100644 --- a/include/arch/xtensa/exc.h +++ b/include/arch/xtensa/exc.h @@ -33,7 +33,6 @@ struct __esf { }; typedef struct __esf NANO_ESF; -extern const NANO_ESF _default_esf; #endif #ifdef __cplusplus diff --git a/include/fatal.h b/include/fatal.h index 34b6092df59..22f2ac9cba8 100644 --- a/include/fatal.h +++ b/include/fatal.h @@ -9,13 +9,6 @@ #include -/* TODO Items: - * - * - Delete default_esf everywhere, just pass a NULL pointer around in that - * situation - * - */ - enum k_fatal_error_reason { /** Generic CPU exception, not covered by other codes */ K_ERR_CPU_EXCEPTION, diff --git a/include/kernel.h b/include/kernel.h index eaa8b3f24e4..38acdff3970 100644 --- a/include/kernel.h +++ b/include/kernel.h @@ -4658,7 +4658,7 @@ extern void z_sys_power_save_idle_exit(s32_t ticks); */ #define z_except_reason(reason) do { \ printk("@ %s:%d:\n", __FILE__, __LINE__); \ - z_fatal_error(reason, &_default_esf); \ + z_fatal_error(reason, NULL); \ } while (false) #endif /* _ARCH__EXCEPT */