soc: espressif: esp32s3: simple boot support
Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej
Anas Nashif
parent
f9008b5330
commit
553238704f
5 changed files with 490 additions and 425 deletions
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@ -1,97 +1,70 @@
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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the ESP32S3 platform.
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg
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start address (that should not be overlapped) */
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#define SRAM_IRAM_END 0x403BA000
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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#include "memory.h"
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#define SRAM_DRAM_START 0x3FC88000
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#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
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#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
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#define ICACHE_SIZE 0x8000
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION ROM
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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/* The "user_iram_end" represents the 2nd stage bootloader
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* "iram_loader_seg" start address (that should not be overlapped).
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* If no bootloader is used, we can extend it to gain more user ram.
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*/
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#ifdef CONFIG_ESP_SIMPLE_BOOT
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user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET);
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#else
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#define FLASH_SIZE 0x800000
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user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
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#endif
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#ifdef CONFIG_BOOTLOADER_ESP_IDF
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#define IROM_SEG_ORG 0x42000020
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#define IROM_SEG_LEN FLASH_SIZE-0x20
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#define IROM_SEG_ALIGN 0x10
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#else
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#define IROM_SEG_ORG 0x42000000
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#define IROM_SEG_LEN FLASH_SIZE
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/* MCUBoot requires MMU page size alignment */
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#define IROM_SEG_ALIGN 0x10000
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#endif
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/* User available SRAM memory segments */
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user_dram_seg_org = SRAM1_DRAM_START;
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user_iram_seg_org = (SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE);
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user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET);
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user_idram_size = (user_dram_end - SRAM1_DRAM_START);
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sram0_iram_size = (SRAM0_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE);
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user_iram_seg_len = (user_idram_size + sram0_iram_size);
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user_dram_seg_len = user_idram_size;
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#ifdef CONFIG_SOC_ENABLE_APPCPU
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#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM
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#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM
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#else
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#define APPCPU_IRAM_SIZE 0x0
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#define APPCPU_DRAM_SIZE 0x0
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#endif
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/* Aliases */
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION FLASH
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/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
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/* Flash segments (rodata and text) should be mapped in the virtual address spaces.
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* Executing directly from LMA is not possible. */
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#undef GROUP_ROM_LINK_IN
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#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
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MEMORY
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{
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mcuboot_hdr (RX): org = 0x0, len = 0x20
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metadata (RX): org = 0x20, len = 0x20
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ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
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iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE
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dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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mcuboot_hdr (R): org = 0x0, len = 0x20
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metadata (R): org = 0x20, len = 0x20
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FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40
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#else
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/* Make safety margin in the FLASH memory size so the
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* (esp_img_header + (n*esp_seg_headers)) would fit */
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FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - APPCPU_IRAM_SIZE
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dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - APPCPU_DRAM_SIZE
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irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
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/* MCUboot binary for ESP32 has image header of 0x20 bytes.
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* Additional load header of 0x20 bytes are appended to the image.
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* Hence, an offset of 0x40 is added to DROM segment origin.
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*/
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drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40
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drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
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/**
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* `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
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* A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
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*/
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#if defined(CONFIG_ESP_SPIRAM)
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ext_ram_seg(RWX): org = 0x3C000040, len = CONFIG_ESP_SPIRAM_SIZE - 0x40
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ext_ram_seg(RWX): org = DROM_SEG_ORG, len = CONFIG_ESP_SPIRAM_SIZE - 0x40
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#endif
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/* RTC fast memory (executable). Persists over deep sleep.
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@ -111,13 +84,17 @@ MEMORY
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#endif
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}
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_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE);
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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/* Used as a pointer to the heap end */
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_heap_sentry = DRAM_BUFFERS_START;
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SECTIONS
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{
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_iram_dram_offset = IRAM_DRAM_OFFSET;
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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/* Reserve space for MCUboot header in the binary */
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.mcuboot_header :
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{
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@ -128,32 +105,37 @@ SECTIONS
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} > mcuboot_hdr
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.metadata :
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{
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/* Magic byte for load header */
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/* 0. Magic byte for load header */
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LONG(0xace637d3)
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/* Application entry point address */
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/* 1. Application entry point address */
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KEEP(*(.entry_addr))
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/* IRAM metadata:
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* - Destination address (VMA) for IRAM region
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* - Flash offset (LMA) for start of IRAM region
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* - Size of IRAM region
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* 2. Destination address (VMA) for IRAM region
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* 3. Flash offset (LMA) for start of IRAM region
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* 4. Size of IRAM region
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*/
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LONG(ADDR(.iram0.vectors))
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LONG(LOADADDR(.iram0.vectors))
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LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))
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/* DRAM metadata:
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* - Destination address (VMA) for DRAM region
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* - Flash offset (LMA) for start of DRAM region
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* - Size of DRAM region
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* 5. Destination address (VMA) for DRAM region
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* 6. Flash offset (LMA) for start of DRAM region
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* 7. Size of DRAM region
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*/
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LONG(ADDR(.dram0.data))
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LONG(LOADADDR(.dram0.data))
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LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
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} > metadata
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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#include <zephyr/linker/rel-sections.ld>
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/* Virtual non-loadable sections */
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#include <zephyr/linker/rel-sections.ld>
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/* --- START OF RTC --- */
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/* RTC fast memory holds RTC wake stub code */
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.rtc.text :
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@ -224,7 +206,7 @@ SECTIONS
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. = ALIGN(4);
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_rtc_force_slow_start = ABSOLUTE(.);
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*(.rtc.force_slow .rtc.force_slow.*)
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. = ALIGN(4) ;
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. = ALIGN(4);
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_rtc_force_slow_end = ABSOLUTE(.);
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} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
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@ -235,6 +217,10 @@ SECTIONS
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ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.")
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ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.")
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/* --- END OF RTC --- */
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/* --- START OF IRAM --- */
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/* Send .iram0 code to iram */
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.iram0.vectors : ALIGN(4)
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{
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@ -365,6 +351,7 @@ SECTIONS
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*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
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*libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*)
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*libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
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*libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*)
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*libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*)
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*libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
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*libzephyr.a:systimer.*(.literal .literal.* .text .text.*)
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@ -377,7 +364,6 @@ SECTIONS
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/* [mapping:esp_rom] */
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*libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*)
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@ -404,25 +390,109 @@ SECTIONS
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*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
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*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
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#endif
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. = ALIGN(4) + 16;
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. = ALIGN(4);
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} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
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/**
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* This section is required to skip .iram0.text area because iram0_0_seg and
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* dram0_0_seg reflect the same address space on different buses.
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*/
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#ifdef CONFIG_ESP_SIMPLE_BOOT
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.loader.text :
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{
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. = ALIGN(4);
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_loader_text_start = ABSOLUTE(.);
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*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_esp32s3.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
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*libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
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*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
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*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
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*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
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*libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*)
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*libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*)
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*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
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*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
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*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
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*libzephyr.a:mpu_hal.*(.literal .text .literal.* .text.*)
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*libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*)
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*(.fini.literal)
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*(.fini)
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. = ALIGN(4);
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_loader_text_end = ABSOLUTE(.);
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} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
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#endif /* CONFIG_ESP_SIMPLE_BOOT */
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */
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. = ALIGN(4) + 16;
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_iram_text_end = ABSOLUTE(.);
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} GROUP_LINK_IN(IRAM_REGION)
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.iram0.data :
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{
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. = ALIGN(4);
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_iram_data_start = ABSOLUTE(.);
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*(.iram.data)
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*(.iram.data*)
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_iram_data_end = ABSOLUTE(.);
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} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_iram_bss_start = ABSOLUTE(.);
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*(.iram.bss)
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*(.iram.bss*)
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_iram_bss_end = ABSOLUTE(.);
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. = ALIGN(4);
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_iram_end = ABSOLUTE(.);
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} GROUP_LINK_IN(IRAM_REGION)
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/* --- END OF IRAM --- */
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/* --- START OF DRAM --- */
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.dram0.dummy (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START;
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/* Spacer section is required to skip .iram0.text area because
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* iram0_0_seg and dram0_0_seg reflect the same address space on different buses.
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*/
|
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. = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START;
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. = ALIGN(4) + 16;
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} GROUP_LINK_IN(RAMABLE_REGION)
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.dram0.data :
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{
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. = ALIGN (8);
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_data_start = ABSOLUTE(.);
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__data_start = ABSOLUTE(.);
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_image_ram_start = ABSOLUTE(.);
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/* bluetooth library requires this symbol to be defined */
|
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_btdm_data_start = ABSOLUTE(.);
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*libbtdm_app.a:(.data .data.*)
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@ -515,6 +585,7 @@ SECTIONS
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*(.rodata.rtc_vddsdio_set_config)
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*libzephyr.a:esp_memory_utils.*(.rodata .rodata.*)
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*libzephyr.a:rtc_clk.*(.rodata .rodata.*)
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*libzephyr.a:rtc_clk_init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:systimer.*(.rodata .rodata.*)
|
||||
*libzephyr.a:mspi_timing_config.*(.rodata .rodata.*)
|
||||
*libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*)
|
||||
|
|
@ -525,7 +596,6 @@ SECTIONS
|
|||
|
||||
/* [mapping:esp_rom] */
|
||||
*libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*)
|
||||
*libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.rodata .rodata.*)
|
||||
*libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*)
|
||||
*libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*)
|
||||
*libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*)
|
||||
|
|
@ -545,12 +615,43 @@ SECTIONS
|
|||
*(.rodata.esp_wifi_bt_power_domain_off)
|
||||
#endif
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#ifdef CONFIG_ESP_SIMPLE_BOOT
|
||||
.loader.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_loader_data_start = ABSOLUTE(.);
|
||||
*libzephyr.a:bootloader_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_flash_config_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:bootloader_efuse.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
|
||||
*libzephyr.a:cpu_util.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
|
||||
*libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
*libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
_loader_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
#endif /* CONFIG_ESP_SIMPLE_BOOT */
|
||||
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
|
|
@ -566,13 +667,11 @@ SECTIONS
|
|||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
__data_end = ABSOLUTE(.);
|
||||
_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
.noinit (NOLOAD):
|
||||
.dram0.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.noinit)
|
||||
|
|
@ -580,7 +679,7 @@ SECTIONS
|
|||
. = ALIGN(4) ;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
/* Shared RAM */
|
||||
.dram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
|
|
@ -608,18 +707,39 @@ SECTIONS
|
|||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/ram-end.ld>
|
||||
.dram0.heap_start (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
/* Lowest possible start address for the heap */
|
||||
_heap_start = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Provide total SRAM usage, including IRAM and DRAM */
|
||||
_image_ram_start = _iram_start - IRAM_DRAM_OFFSET;
|
||||
#include <zephyr/linker/ram-end.ld>
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
|
||||
|
||||
/* --- END OF DRAM --- */
|
||||
|
||||
/* --- START OF IROM --- */
|
||||
|
||||
/* Symbols used during the application memory mapping */
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
/* Align next section to 64k to allow mapping */
|
||||
.flash.text_dummy (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(CACHE_ALIGN);
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
.flash.text : ALIGN(0x10)
|
||||
{
|
||||
_stext = .;
|
||||
_instruction_reserved_start = ABSOLUTE(.);
|
||||
|
|
@ -628,7 +748,6 @@ SECTIONS
|
|||
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
|
|
@ -658,35 +777,30 @@ SECTIONS
|
|||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
//_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
/**
|
||||
* This dummy section represents the .flash.text section but in default_rodata_seg.
|
||||
/* This dummy section represents the .flash.text section but in default_rodata_seg.
|
||||
* Thus, it must have its alignment and (at least) its size.
|
||||
*/
|
||||
.flash_rodata_dummy (NOLOAD):
|
||||
.flash.rodata_dummy (NOLOAD):
|
||||
{
|
||||
_flash_rodata_dummy_start = ABSOLUTE(.);
|
||||
/* Start at the same alignment constraint than .flash.text */
|
||||
. = ALIGN(ALIGNOF(.flash.text));
|
||||
/* Create an empty gap as big as .flash.text section */
|
||||
. = . + SIZEOF(.flash.text);
|
||||
/* Prepare the alignment of the section above. Few bytes (0x20) must be
|
||||
* added for the mapping header. */
|
||||
. = ALIGN(_esp_mmu_block_size) + 0x40;
|
||||
. += SIZEOF(.flash.text);
|
||||
. = ALIGN(CACHE_ALIGN);
|
||||
} GROUP_LINK_IN(RODATA_REGION)
|
||||
|
||||
_image_drom_start = LOADADDR(.flash.rodata);
|
||||
_image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(.flash.rodata);
|
||||
|
||||
.flash.rodata : ALIGN(IROM_SEG_ALIGN)
|
||||
.flash.rodata : ALIGN(CACHE_ALIGN)
|
||||
{
|
||||
_flash_rodata_start = ABSOLUTE(.);
|
||||
_rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
|
|
@ -727,6 +841,7 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
|
|
@ -755,7 +870,7 @@ SECTIONS
|
|||
.ext_ram.dummy (NOLOAD):
|
||||
{
|
||||
. = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
|
||||
. = ALIGN (0x10000);
|
||||
. = ALIGN (CACHE_ALIGN);
|
||||
} GROUP_LINK_IN(ext_ram_seg)
|
||||
|
||||
/* This section holds .ext_ram.bss data, and will be put in PSRAM */
|
||||
|
|
@ -774,48 +889,11 @@ SECTIONS
|
|||
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
|
||||
/* Marks the end of IRAM code segment */
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */
|
||||
. += 16;
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_iram_data_start = ABSOLUTE(.);
|
||||
*(.iram.data)
|
||||
*(.iram.data*)
|
||||
_iram_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_iram_bss_start = ABSOLUTE(.);
|
||||
*(.iram.bss)
|
||||
*(.iram.bss*)
|
||||
_iram_bss_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
/* Marks the end of data, bss and possibly rodata */
|
||||
.dram0.heap_start (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
/* Lowest possible start address for the heap */
|
||||
_heap_start = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
_heap_sentry = 0x3fceb910;
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue