diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt index 0a261dbe1e0..540881b45ab 100644 --- a/soc/espressif/esp32s3/CMakeLists.txt +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -19,44 +19,31 @@ zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) zephyr_library_sources_ifdef(CONFIG_PM power.c) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) -# get flash size to use in esptool as string +# Get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") -if(CONFIG_BOOTLOADER_ESP_IDF) - - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) +# Make rom loader compatible binary file +if(NOT CONFIG_BOOTLOADER_MCUBOOT) if(CONFIG_BUILD_OUTPUT_BIN) + + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") + + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32s3 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m + --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) endif() - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - endif() ## When building for APPCPU @@ -74,17 +61,19 @@ else() set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address + # Get code-partition boot address dt_nodelabel(dts_partition_path NODELABEL "boot_partition") dt_reg_addr(boot_off PATH ${dts_partition_path}) - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + # Get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + if(NOT CONFIG_BOOTLOADER_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") + else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + endif() endif() diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 3a9aa37794d..120fb083d38 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -1,97 +1,70 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the ESP32S3 platform. - */ - #include #include #include #include -#define SRAM_IRAM_START 0x40370000 -#define SRAM_DIRAM_I_START 0x40378000 -/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_IRAM_END 0x403BA000 -#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) +#include "memory.h" -#define SRAM_DRAM_START 0x3FC88000 -#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) - -#define ICACHE_SIZE 0x8000 -#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) - -#define SRAM_DRAM_ORG (SRAM_DRAM_START) - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION ROM - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE +/* The "user_iram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET); #else -#define FLASH_SIZE 0x800000 +user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#define IROM_SEG_ALIGN 0x10 -#else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -/* MCUBoot requires MMU page size alignment */ -#define IROM_SEG_ALIGN 0x10000 -#endif +/* User available SRAM memory segments */ +user_dram_seg_org = SRAM1_DRAM_START; +user_iram_seg_org = (SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE); +user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET); +user_idram_size = (user_dram_end - SRAM1_DRAM_START); +sram0_iram_size = (SRAM0_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE); +user_iram_seg_len = (user_idram_size + sram0_iram_size); +user_dram_seg_len = user_idram_size; -#ifdef CONFIG_SOC_ENABLE_APPCPU -#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM -#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM -#else -#define APPCPU_IRAM_SIZE 0x0 -#define APPCPU_DRAM_SIZE 0x0 -#endif +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. +/* Flash segments (rodata and text) should be mapped in the virtual address spaces. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ + + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - APPCPU_IRAM_SIZE + dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - APPCPU_DRAM_SIZE irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - - /* MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN /** * `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region. * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` */ #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = 0x3C000040, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 + ext_ram_seg(RWX): org = DROM_SEG_ORG, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 #endif /* RTC fast memory (executable). Persists over deep sleep. @@ -111,13 +84,17 @@ MEMORY #endif } -_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE); - /* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) +/* Used as a pointer to the heap end */ +_heap_sentry = DRAM_BUFFERS_START; + SECTIONS { + _iram_dram_offset = IRAM_DRAM_OFFSET; + +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -128,32 +105,37 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ LONG(ADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - #include + +/* Virtual non-loadable sections */ +#include + + /* --- START OF RTC --- */ /* RTC fast memory holds RTC wake stub code */ .rtc.text : @@ -224,7 +206,7 @@ SECTIONS . = ALIGN(4); _rtc_force_slow_start = ABSOLUTE(.); *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; + . = ALIGN(4); _rtc_force_slow_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) @@ -235,6 +217,10 @@ SECTIONS ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ + /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) { @@ -365,6 +351,7 @@ SECTIONS *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*) *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) @@ -377,7 +364,6 @@ SECTIONS /* [mapping:esp_rom] */ *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) @@ -404,25 +390,109 @@ SECTIONS *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) #endif - - . = ALIGN(4) + 16; + . = ALIGN(4); } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : + { + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32s3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:mpu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + *(.fini.literal) + *(.fini) + + . = ALIGN(4); + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . = ALIGN(4) + 16; + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : + { + . = ALIGN(4); + _iram_data_start = ABSOLUTE(.); + *(.iram.data) + *(.iram.data*) + _iram_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss*) + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + /* --- END OF IRAM --- */ + + /* --- START OF DRAM --- */ + .dram0.dummy (NOLOAD): { - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; + /* Spacer section is required to skip .iram0.text area because + * iram0_0_seg and dram0_0_seg reflect the same address space on different buses. + */ + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START; + . = ALIGN(4) + 16; } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : { . = ALIGN (8); + _data_start = ABSOLUTE(.); __data_start = ABSOLUTE(.); - _image_ram_start = ABSOLUTE(.); + /* bluetooth library requires this symbol to be defined */ _btdm_data_start = ABSOLUTE(.); *libbtdm_app.a:(.data .data.*) @@ -515,6 +585,7 @@ SECTIONS *(.rodata.rtc_vddsdio_set_config) *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*) *libzephyr.a:systimer.*(.rodata .rodata.*) *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) @@ -525,7 +596,6 @@ SECTIONS /* [mapping:esp_rom] */ *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) - *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.rodata .rodata.*) *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) @@ -545,12 +615,43 @@ SECTIONS *(.rodata.esp_wifi_bt_power_domain_off) #endif + . = ALIGN(4); + #include + . = ALIGN(4); + KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash_config_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_efuse.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cpu_util.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + . = ALIGN(4); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + #include #include #include @@ -566,13 +667,11 @@ SECTIONS .dram0.end : { - . = ALIGN(4); - #include - . = ALIGN(4); __data_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - .noinit (NOLOAD): + .dram0.noinit (NOLOAD): { . = ALIGN(4); *(.noinit) @@ -580,7 +679,7 @@ SECTIONS . = ALIGN(4) ; } GROUP_LINK_IN(RAMABLE_REGION) - /* Shared RAM */ + /* Shared RAM */ .dram0.bss (NOLOAD) : { . = ALIGN (8); @@ -608,18 +707,39 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN (8); + _bss_end = ABSOLUTE(.); __bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) -#include + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (8); + /* Lowest possible start address for the heap */ + _heap_start = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + /* --- END OF DRAM --- */ + + /* --- START OF IROM --- */ + + /* Symbols used during the application memory mapping */ _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash.text : ALIGN(IROM_SEG_ALIGN) + /* Align next section to 64k to allow mapping */ + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + .flash.text : ALIGN(0x10) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); @@ -628,7 +748,6 @@ SECTIONS #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) - #endif #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -658,35 +777,30 @@ SECTIONS * resolved by addr2line in preference to the first symbol in * the flash.text segment. */ - _flash_cache_start = ABSOLUTE(0); + //_flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - /** - * This dummy section represents the .flash.text section but in default_rodata_seg. + /* This dummy section represents the .flash.text section but in default_rodata_seg. * Thus, it must have its alignment and (at least) its size. */ - .flash_rodata_dummy (NOLOAD): + .flash.rodata_dummy (NOLOAD): { _flash_rodata_dummy_start = ABSOLUTE(.); - /* Start at the same alignment constraint than .flash.text */ - . = ALIGN(ALIGNOF(.flash.text)); - /* Create an empty gap as big as .flash.text section */ - . = . + SIZEOF(.flash.text); - /* Prepare the alignment of the section above. Few bytes (0x20) must be - * added for the mapping header. */ - . = ALIGN(_esp_mmu_block_size) + 0x40; + . += SIZEOF(.flash.text); + . = ALIGN(CACHE_ALIGN); } GROUP_LINK_IN(RODATA_REGION) _image_drom_start = LOADADDR(.flash.rodata); _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; _image_drom_vaddr = ADDR(.flash.rodata); - .flash.rodata : ALIGN(IROM_SEG_ALIGN) + .flash.rodata : ALIGN(CACHE_ALIGN) { _flash_rodata_start = ABSOLUTE(.); _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ _rodata_start = ABSOLUTE(.); __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); #include @@ -727,6 +841,7 @@ SECTIONS . = ALIGN(4); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + #include #include #include #include @@ -755,7 +870,7 @@ SECTIONS .ext_ram.dummy (NOLOAD): { . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); - . = ALIGN (0x10000); + . = ALIGN (CACHE_ALIGN); } GROUP_LINK_IN(ext_ram_seg) /* This section holds .ext_ram.bss data, and will be put in PSRAM */ @@ -774,48 +889,11 @@ SECTIONS #endif /* CONFIG_ESP_SPIRAM */ - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ - . += 16; - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(4); - _iram_data_start = ABSOLUTE(.); - *(.iram.data) - *(.iram.data*) - _iram_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(4); - _iram_bss_start = ABSOLUTE(.); - *(.iram.bss) - *(.iram.bss*) - _iram_bss_end = ABSOLUTE(.); - . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - /* Marks the end of data, bss and possibly rodata */ - .dram0.heap_start (NOLOAD) : - { - . = ALIGN (8); - /* Lowest possible start address for the heap */ - _heap_start = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) #ifdef CONFIG_GEN_ISR_TABLES #include #endif -_heap_sentry = 0x3fceb910; - #include .xtensa.info 0 : { *(.xtensa.info) } diff --git a/soc/espressif/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld index b562192a625..01ad3aded33 100644 --- a/soc/espressif/esp32s3/mcuboot.ld +++ b/soc/espressif/esp32s3/mcuboot.ld @@ -1,20 +1,15 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "Xtensa bootloader cannot use XIP" #endif /* CONFIG_XIP */ @@ -23,52 +18,19 @@ #undef GROUP_DATA_LINK_IN #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion -#define RAMABLE_REGION dram_seg -#define RAMABLE_REGION_1 dram_seg +/* Aliases for zephyr scripts */ +#define RAMABLE_REGION dram_seg +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg -#define RODATA_REGION dram_seg -#define ROMABLE_REGION dram_seg - -#define IRAM_REGION iram_seg -#define FLASH_CODE_REGION iram_seg - -#define IROM_SEG_ALIGN 16 - -/** Simplified memory map for the bootloader. - * Make sure the bootloader can load into main memory without overwriting itself. - * - * ESP32-S3 ROM static data usage is as follows: - * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) - * - * The 2nd stage bootloader can take space up to the end of ROM shared - * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). - */ -/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ -iram_dram_offset = 0x6f0000; - -bootloader_usable_dram_end = 0x3fce9700; - -bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ -bootloader_dram_seg_len = 0x6600; -bootloader_iram_loader_seg_len = 0x3000; -bootloader_iram_seg_len = 0x9000; - -/* Start of the lower region is determined by region size and the end of the higher region */ -bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; -/* bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; */ -/* We move the dram start to 0x3FCA0000 */ -bootloader_dram_seg_start = 0x3FCA0000; -bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; -bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; +_bootloader_dram_seg_end = BOOTLOADER_DRAM_SEG_END; +_bootloader_iram_loader_seg_start = BOOTLOADER_IRAM_LOADER_SEG_START; MEMORY { - iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len - iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len - dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len + iram_seg (RWX) : org = BOOTLOADER_IRAM_SEG_START, len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RWX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -80,14 +42,148 @@ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + .iram0.loader_text : { - __rodata_region_start = ABSOLUTE(.); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*) + *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*) + *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*) + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) + + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + *libkernel.a:device.*(.literal .text .literal.* .text.*) + *libkernel.a:timeout.*(.literal .text .literal.* .text.*) + + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) + + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; . = ALIGN(4); + _loader_text_end = ABSOLUTE(.); + _iram_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN (4); + _init_end = ABSOLUTE(.); + + /* This goes here, not at top of linker script, so addr2line finds it last, + * and uses it in preference to the first symbol in IRAM + */ + _iram_start = ABSOLUTE(.); + } > iram_seg + + .iram0.text : + { + . = ALIGN(4); + + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + . = ALIGN(4); + } > iram_seg + + .dram0.data : ALIGN(16) + { + . = ALIGN(4); + __data_start = ABSOLUTE(.); + #include + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) . = ALIGN(4); *(.rodata) *(.rodata.*) @@ -125,37 +221,14 @@ SECTIONS *(.rodata_wlog) *(.rodata_wlog*) _thread_local_end = ABSOLUTE(.); - /* _rodata_reserved_end = ABSOLUTE(.); */ . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + } > dram_seg #include #include #include #include - .dram0.data : - { - __data_start = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include #include #include @@ -163,124 +236,16 @@ SECTIONS #include #include - .dram0.end : + .noinit (NOLOAD): { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - _heap_sentry = .; - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) - { - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - _invalid_pc_placeholder = ABSOLUTE(.); - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - * and uses it in preference to the first symbol in IRAM - */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) - *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); */ - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ @@ -304,49 +269,10 @@ SECTIONS __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + } > dram_seg ASSERT(((__bss_end - ORIGIN(dram_seg)) <= LENGTH(dram_seg)), "DRAM segment data does not fit.") - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - - .flash.text : - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - #include .xtensa.info 0 : { *(.xtensa.info) } @@ -386,8 +312,4 @@ SECTIONS #ifdef CONFIG_GEN_ISR_TABLES #include #endif - } - -ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), - "IRAM0 segment data does not fit.") diff --git a/soc/espressif/esp32s3/memory.h b/soc/espressif/esp32s3/memory.h new file mode 100644 index 00000000000..5675acccead --- /dev/null +++ b/soc/espressif/esp32s3/memory.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (64k), SRAM1 (416k), SRAM2 (64k) memories + * Ibus and Dbus address space + */ +#define SRAM0_IRAM_START 0x40370000 +#define SRAM0_SIZE 0x8000 +#define SRAM1_DRAM_START 0x3fc88000 +/* IRAM equivalent address where DRAM actually start */ +#define SRAM1_IRAM_START (SRAM0_IRAM_START + SRAM0_SIZE) +#define SRAM2_DRAM_START 0x3fcf0000 +#define SRAM2_SIZE 0x10000 + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-S3 ROM static data usage is as follows: + * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). + */ + +/* The offset between Dbus and Ibus. + * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. + */ +#define IRAM_DRAM_OFFSET 0x6f0000 +#define DRAM_BUFFERS_START 0x3fcd7e00 +#define DRAM_PROCPU_STACK_START 0x3fce9710 +#define DRAM_STACK_START DRAM_PROCPU_STACK_START +#define DRAM_APPCPU_STACK_START 0x3fceb710 +#define DRAM_ROM_BSS_DATA_START 0x3fcf0000 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +#define BOOTLOADER_DRAM_SEG_LEN 0x6600 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x2c00 +#define BOOTLOADER_IRAM_SEG_LEN 0x9000 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END - BOOTLOADER_STACK_OVERHEAD) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \ + BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x800000 +#endif + +/* Cached memory */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define DROM_SEG_ORG 0x3c000000 +#define DROM_SEG_LEN FLASH_SIZE + +/* AMP */ +#ifdef CONFIG_SOC_ENABLE_APPCPU +#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM +#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM +#else +#define APPCPU_IRAM_SIZE 0 +#define APPCPU_DRAM_SIZE 0 +#endif diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index 54af1c4d20b..c63d61474dd 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -143,12 +143,7 @@ void IRAM_ATTR __esp_platform_start(void) */ __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else +#ifndef CONFIG_MCUBOOT /* Configure the mode of instruction cache : cache size, cache line size. */ esp_config_instruction_cache_mode(); @@ -189,6 +184,7 @@ void IRAM_ATTR __esp_platform_start(void) (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* CONFIG_ESP_SPIRAM */ + /* Apply SoC patches */ esp_errata(); @@ -216,7 +212,7 @@ void IRAM_ATTR __esp_platform_start(void) #if CONFIG_SOC_FLASH_ESP32 spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ esp_intr_initialize();