From 530b593275b46b9e6978c0c1509696f23912aebf Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 9 May 2024 11:10:51 -0400 Subject: [PATCH] arch: riscv: apply CONFIG_RISCV_MCAUSE_EXCEPTION_MASK to FPU code Some implementations use bits outside of the mcause mask for other purpose. Signed-off-by: Nicolas Pitre --- arch/riscv/core/isr.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index 2a8ed28deae..e9a3d523127 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -203,6 +203,8 @@ SECTION_FUNC(exception.entry, _isr_wrapper) bnez t1, no_fp /* determine if this is an Illegal Instruction exception */ csrr t2, mcause + li t1, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK + and t2, t2, t1 li t1, 2 /* 2 = illegal instruction */ bne t1, t2, no_fp /* determine if we trapped on an FP instruction. */