michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc/intel_adsp: Fix ATOMCTL on MP startup

Browse source 
Hardware defaults for the secondary CPUs have the S32C1I instruction
set to be atomic only with respect to the local L1 cache, which is
basically useless on a multiprocessor platform.  The CPU0 boot path
sets this manually, so we need to duplicate that here.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-08-05 13:51:16 -07:00 • committed by Anas Nashif
commit 52a7c562cb
1 changed files with 9 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

10
soc/xtensa/intel_adsp/common/soc_mp.c
View file

@ -120,7 +120,15 @@ int cavs_idc_smp_init(const struct device *dev);
void z_mp_entry(void)
{
volatile int ie;
uint32_t idc_reg;
uint32_t idc_reg, reg;
/* Fix ATOMCTL to match CPU0. Hardware defaults for S32C1I
* use internal operations (and are thus presumably atomic
* only WRT the local CPU!). We need external transactions on
* the shared bus
*/
reg = 0x15;
__asm__ volatile("wsr %0, ATOMCTL" :: "r"(reg));
/* Correct the Region Protection Option cachability settings.
* The hardware defaults (everything accessible and uncached)