From 52a7c562cbc2b6ca2bfc2d164b67868698104197 Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 5 Aug 2021 13:51:16 -0700 Subject: [PATCH] soc/intel_adsp: Fix ATOMCTL on MP startup Hardware defaults for the secondary CPUs have the S32C1I instruction set to be atomic only with respect to the local L1 cache, which is basically useless on a multiprocessor platform. The CPU0 boot path sets this manually, so we need to duplicate that here. Signed-off-by: Andy Ross --- soc/xtensa/intel_adsp/common/soc_mp.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 24bf80c65b9..c7587faee2a 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -120,7 +120,15 @@ int cavs_idc_smp_init(const struct device *dev); void z_mp_entry(void) { volatile int ie; - uint32_t idc_reg; + uint32_t idc_reg, reg; + + /* Fix ATOMCTL to match CPU0. Hardware defaults for S32C1I + * use internal operations (and are thus presumably atomic + * only WRT the local CPU!). We need external transactions on + * the shared bus + */ + reg = 0x15; + __asm__ volatile("wsr %0, ATOMCTL" :: "r"(reg)); /* Correct the Region Protection Option cachability settings. * The hardware defaults (everything accessible and uncached)