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boards: frdm_mcxn947: Add support for the QSPI flash

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Add support for the QSPI flash connected over FlexSPI

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2024-03-19 14:49:00 -05:00 • committed by Anas Nashif
commit 517753e475
5 changed files with 77 additions and 0 deletions
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8
boards/nxp/frdm_mcxn947/board.c
View file

@ -6,6 +6,7 @@
#include <zephyr/device.h> #include <zephyr/device.h>
#include <fsl_clock.h> #include <fsl_clock.h>
#include <fsl_spc.h> #include <fsl_spc.h>
#include <soc.h>
/* Board xtal frequency in Hz */ /* Board xtal frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U #define BOARD_XTAL0_CLK_HZ 24000000U
@ -66,6 +67,13 @@ static int frdm_mcxn947_init(void)
/* Enable FRO HF(48MHz) output */ /* Enable FRO HF(48MHz) output */
CLOCK_SetupFROHFClocking(48000000U); CLOCK_SetupFROHFClocking(48000000U);
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
/* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable
* clock source when updating the PLL if in XIP (execute code from FlexSPI memory
*/
flexspi_clock_safe_config();
#endif
/* Set up PLL0 */ /* Set up PLL0 */
const pll_setup_t pll0Setup = { const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |

2
boards/nxp/frdm_mcxn947/doc/index.rst
View file

@ -63,6 +63,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash | | FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
Targets available Targets available
================== ==================

21
boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi
View file

@ -16,4 +16,25 @@
input-enable; input-enable;
}; };
}; };
pinmux_flexspi: pinmux_flexspi {
group0 {
pinmux = <FLEXSPI0_A_SS0_b_PIO3_0>,
<FLEXSPI0_A_SCLK_PIO3_7>,
<FLEXSPI0_A_DQS_PIO3_6>,
<FLEXSPI0_A_DATA0_PIO3_8>,
<FLEXSPI0_A_DATA1_PIO3_9>;
input-enable;
slew-rate = "fast";
drive-strength = "low";
};
group1 {
pinmux = <FLEXSPI0_A_DATA2_PIO3_10>,
<FLEXSPI0_A_DATA3_PIO3_11>;
input-enable;
slew-rate = "fast";
drive-strength = "low";
bias-pull-up;
};
};
}; };

38
boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi
View file

@ -88,3 +88,41 @@
}; };
}; };
}; };
&flexspi {
pinctrl-0 = <&pinmux_flexspi>;
pinctrl-names = "default";
ahb-prefetch;
ahb-bufferable;
ahb-cacheable;
ahb-read-addr-opt;
combination-mode;
rx-clock-source = <1>;
/* WINBOND flash memory*/
w25q64jvssiq: w25q64jvssiq@0 {
compatible = "nxp,imx-flexspi-nor";
status = "disabled";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
jedec-id = [ef 40 17];
erase-block-size = <4096>;
write-block-size = <1>;
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <3>;
cs-setup-time = <3>;
data-valid-time = <2>;
column-space = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x0 DT_SIZE_M(8)>;
};
};
};
};

8
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts
View file

@ -72,3 +72,11 @@
&flexcomm4_lpuart4 { &flexcomm4_lpuart4 {
status = "okay"; status = "okay";
}; };
&flexspi {
status = "okay";
};
&w25q64jvssiq {
status = "okay";
};