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drivers: flash: stm32: Update flash driver implementation

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Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.

Fixes #16235

Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
This commit is contained in:
Sarvesh Patkar 2019-11-16 14:34:13 -08:00 • committed by Maureen Helm
commit 4f2c107389
20 changed files with 156 additions and 714 deletions
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52
soc/arm/st_stm32/stm32f0/flash_registers.h
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@ -1,52 +0,0 @@
/*
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F0X_FLASH_REGISTERS_H_
#define _STM32F0X_FLASH_REGISTERS_H_
#include <zephyr/types.h>
/**
* @brief
*
* Based on reference manual:
* STM32F030x4/x6/x8/xC,
* STM32F070x6/xB advanced ARM ® -based MCUs
*
* Chapter 3.3.5: Embedded Flash Memory
*/
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1
};
/* 3.3.5.1 FLASH_ACR */
union ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3 :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.5 Embedded flash registers */
struct stm32f0x_flash {
volatile union ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
#endif /* _STM32F0X_FLASH_REGISTERS_H_ */

51
soc/arm/st_stm32/stm32f1/flash_registers.h
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@ -1,51 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F10X_FLASH_REGISTERS_H_
#define _STM32F10X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3.3.3: Embedded Flash Memory
*/
enum {
STM32F10X_FLASH_LATENCY_0 = 0x0,
STM32F10X_FLASH_LATENCY_1 = 0x1,
STM32F10X_FLASH_LATENCY_2 = 0x2,
};
/* 3.3.3 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32f1x_flash {
volatile union __ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
#endif /* _STM32F10X_FLASHREGISTERS_H_ */

60
soc/arm/st_stm32/stm32f3/flash_registers.h
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@ -1,60 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F3X_FLASH_REGISTERS_H_
#define _STM32F3X_FLASH_REGISTERS_H_
#include <zephyr/types.h>
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
* &
* STM32F334xx advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3.3.3: Embedded Flash Memory
*/
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1,
STM32_FLASH_LATENCY_2 = 0x2,
};
/* 3.3.3 FLASH_ACR */
union ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32f3x_flash {
volatile union ef_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t ar;
volatile u32_t rsvd;
volatile u32_t obr;
volatile u32_t wrpr;
};
/* list of device commands */
enum stm32_embedded_flash_cmd {
STM32_FLASH_CMD_LATENCY_FOR_CLOCK_SET,
};
#endif /* _STM32F3X_FLASH_REGISTERS_H_ */

42
soc/arm/st_stm32/stm32f4/flash_registers.h
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/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F4X_FLASH_REGISTERS_H_
#define _STM32F4X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
*
* Chapter 3.4: Embedded Flash Memory
*/
union __flash_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t rsvd__13_31 :19 __packed;
} bit;
};
/* 3.8.7 Embedded flash registers */
struct stm32f4x_flash {
volatile union __flash_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t optcr;
};
#endif /* _STM32F4X_FLASHREGISTERS_H_ */

44
soc/arm/st_stm32/stm32f7/flash_registers.h
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/*
* Copyright (c) 2018 Yurii Hamann
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F7X_FLASH_REGISTERS_H_
#define _STM32F7X_FLASH_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* RM0385 Reference manual STM32F75xxx and STM32F74xxx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 3: Embedded Flash Memory
*/
union __flash_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t arten :1 __packed;
u32_t rsvd__10 :1 __packed;
u32_t artrst :1 __packed;
u32_t rsvd__12_31 :20 __packed;
} bit;
};
/* 3.7 FLASH registers */
struct stm32f7x_flash {
volatile union __flash_acr acr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t optcr;
volatile u32_t optcr1;
};
#endif /* _STM32F7X_FLASHREGISTERS_H_ */

53
soc/arm/st_stm32/stm32g0/flash_registers.h
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/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32G0X_FLASH_REGISTERS_H_
#define _STM32G0X_FLASH_REGISTERS_H_
#define FLASH_SR_BSY FLASH_SR_BSY1
enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1,
STM32_FLASH_LATENCY_2 = 0x2,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t rsvd__10 :1 __packed;
u32_t icrst :1 __packed;
u32_t rsvd__12_15 :4 __packed;
u32_t empty :1 __packed;
u32_t rsvd__17 :1 __packed;
u32_t dbg_swend :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};
/* FLASH register map */
struct stm32g0x_flash {
volatile union __ef_acr acr;
volatile u32_t rsvd__4;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
};
#endif /* _STM32G0X_FLASH_REGISTERS_H_ */

67
soc/arm/st_stm32/stm32g4/flash_registers.h
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/*
* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32G4X_FLASH_REGISTERS_H_
#define _STM32G4X_FLASH_REGISTERS_H_
enum {
STM32G4X_FLASH_LATENCY_0 = 0x0,
STM32G4X_FLASH_LATENCY_1 = 0x1,
STM32G4X_FLASH_LATENCY_2 = 0x2,
STM32G4X_FLASH_LATENCY_3 = 0x3,
STM32G4X_FLASH_LATENCY_4 = 0x4,
STM32G4X_FLASH_LATENCY_5 = 0x5,
STM32G4X_FLASH_LATENCY_6 = 0x6,
STM32G4X_FLASH_LATENCY_7 = 0x7,
STM32G4X_FLASH_LATENCY_8 = 0x8,
STM32G4X_FLASH_LATENCY_9 = 0x9,
STM32G4X_FLASH_LATENCY_10 = 0x10,
STM32G4X_FLASH_LATENCY_11 = 0x11,
STM32G4X_FLASH_LATENCY_12 = 0x12,
STM32G4X_FLASH_LATENCY_13 = 0x13,
STM32G4X_FLASH_LATENCY_14 = 0x14,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__15_17 :3 __packed;
u32_t dbg_swend :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};
/* 3.7.13 Embedded flash registers */
struct stm32g4x_flash {
volatile union __ef_acr acr;
volatile u32_t pdkeyr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t pcrop2sr;
volatile u32_t pcrop2er;
volatile u32_t wrp2ar;
volatile u32_t wrp2br;
};
#endif /* _STM32G4X_FLASH_REGISTERS_H_ */

63
soc/arm/st_stm32/stm32l4/flash_registers.h
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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_FLASH_REGISTERS_H_
#define _STM32L4X_FLASH_REGISTERS_H_
enum {
STM32L4X_FLASH_LATENCY_0 = 0x0,
STM32L4X_FLASH_LATENCY_1 = 0x1,
STM32L4X_FLASH_LATENCY_2 = 0x2,
STM32L4X_FLASH_LATENCY_3 = 0x3,
STM32L4X_FLASH_LATENCY_4 = 0x4,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__16_31 :17 __packed;
} bit;
};
/* FLASH register map */
struct stm32l4x_flash {
volatile union __ef_acr acr;
volatile u32_t pdkeyr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t rsvd_2[4];
/*
* The registers below are only present on STM32L4x2, STM32L4x5,
* STM32L4x6.
*/
volatile u32_t pcrop2sr;
volatile u32_t pcrop2er;
volatile u32_t wrp2ar;
volatile u32_t wrp2br;
};
#endif /* _STM32L4X_FLASH_REGISTERS_H_ */

63
soc/arm/st_stm32/stm32wb/flash_registers.h
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/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32WBX_FLASH_REGISTERS_H_
#define _STM32WBX_FLASH_REGISTERS_H_
enum {
STM32WBX_FLASH_LATENCY_0 = 0x0,
STM32WBX_FLASH_LATENCY_1 = 0x1,
STM32WBX_FLASH_LATENCY_2 = 0x2,
STM32WBX_FLASH_LATENCY_3 = 0x3,
STM32WBX_FLASH_LATENCY_4 = 0x4,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t rsvd__13_14 :2 __packed;
u32_t pes :1 __packed;
u32_t empty :1 __packed;
u32_t rsvd__17_31 :15 __packed;
} bit;
};
/* FLASH register map */
struct stm32wbx_flash {
volatile union __ef_acr acr;
volatile u32_t rsvd_0;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_1;
volatile u32_t optr;
volatile u32_t pcrop1asr;
volatile u32_t pcrop1aer;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t pcrop1bsr;
volatile u32_t pcrop1ber;
volatile u32_t ipccbr;
volatile u32_t rsvd_2[8];
volatile u32_t c2acr;
volatile u32_t c2sr;
volatile u32_t c2cr;
volatile u32_t rsvd_3[7];
volatile u32_t sfr;
volatile u32_t srrvr;
};
#endif /* _STM32WBX_FLASH_REGISTERS_H_ */