70d819b405
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
63 lines
1.3 KiB
C
63 lines
1.3 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32L4X_FLASH_REGISTERS_H_
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#define _STM32L4X_FLASH_REGISTERS_H_
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enum {
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STM32L4X_FLASH_LATENCY_0 = 0x0,
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STM32L4X_FLASH_LATENCY_1 = 0x1,
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STM32L4X_FLASH_LATENCY_2 = 0x2,
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STM32L4X_FLASH_LATENCY_3 = 0x3,
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STM32L4X_FLASH_LATENCY_4 = 0x4,
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};
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/* 3.7.1 FLASH_ACR */
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union __ef_acr {
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u32_t val;
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struct {
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u32_t latency :3 __packed;
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u32_t rsvd__3_7 :5 __packed;
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u32_t prften :1 __packed;
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u32_t icen :1 __packed;
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u32_t dcen :1 __packed;
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u32_t icrst :1 __packed;
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u32_t dcrst :1 __packed;
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u32_t run_pd :1 __packed;
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u32_t sleep_pd :1 __packed;
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u32_t rsvd__16_31 :17 __packed;
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} bit;
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};
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/* FLASH register map */
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struct stm32l4x_flash {
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volatile union __ef_acr acr;
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volatile u32_t pdkeyr;
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volatile u32_t keyr;
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volatile u32_t optkeyr;
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volatile u32_t sr;
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volatile u32_t cr;
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volatile u32_t eccr;
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volatile u32_t rsvd_0;
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volatile u32_t optr;
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volatile u32_t pcrop1sr;
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volatile u32_t pcrop1er;
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volatile u32_t wrp1ar;
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volatile u32_t wrp1br;
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volatile u32_t rsvd_2[4];
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/*
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* The registers below are only present on STM32L4x2, STM32L4x5,
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* STM32L4x6.
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*/
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volatile u32_t pcrop2sr;
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volatile u32_t pcrop2er;
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volatile u32_t wrp2ar;
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volatile u32_t wrp2br;
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};
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#endif /* _STM32L4X_FLASH_REGISTERS_H_ */
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