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DTS: intel_s1000: Clean up I2C and UART stuff from soc.h

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Clean up some remnant stuff related to I2C and UART from soc.h
and put it in dts.fixup

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This commit is contained in:
Rajavardhan Gundi 2018-05-30 12:41:59 +05:30 • committed by Anas Nashif
commit 4ec773f276
2 changed files with 7 additions and 18 deletions
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13
arch/xtensa/soc/intel_s1000/dts.fixup
View file

@ -3,11 +3,12 @@
#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL #define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ (NS16550_80800_IRQ_0 << 16) | \ #define CONFIG_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0) (INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS #define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
@ -39,9 +40,9 @@
#define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS #define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
#define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY #define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL #define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL
#define CONFIG_I2C_0_IRQ (SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \ #define CONFIG_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0) (INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE #define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY #define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY

12
arch/xtensa/soc/intel_s1000/soc.h
View file

@ -43,18 +43,6 @@
#define GPIO_DW_0_IRQ 0x00040706 #define GPIO_DW_0_IRQ 0x00040706
#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ) #define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ)
/* UART - UART0 */
#define CONFIG_UART_NS16550_P0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(\
NS16550_80800_IRQ_0)
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0
/* I2C - I2C0 */
#define I2C_DW_0_BASE_ADDR 0x00080400
#define I2C_DW_0_IRQ 0x00020706
#define I2C_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(I2C_DW_0_IRQ)
#define I2C_DW_IRQ_FLAGS 0
#define I2C_DW_CLOCK_SPEED 38
/* low power DMACs */ /* low power DMACs */
#define LP_GP_DMA_SIZE 0x00001000 #define LP_GP_DMA_SIZE 0x00001000
#define DW_DMA0_BASE_ADDR 0x0007C000 #define DW_DMA0_BASE_ADDR 0x0007C000