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arm: exx32: Add Silabs EFM32JG12B soc files

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The Silicon Labs EFM32 Jade Gecko MCU includes:

    * Cortex-M3 core at 40MHz
    * up to 1024KB of flash and 256KB of RAM
    * multiple low power peripherals

This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
This commit is contained in:
Christian Taedcke 2019-12-04 10:38:47 +01:00 • committed by Kumar Gala
commit 4ead400d79
14 changed files with 427 additions and 176 deletions
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187
dts/arm/silabs/efm32_jg_pg_12b.dtsi Normal file
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/*
* Copyright (c) 2018 Christian Taedcke <hacking@taedcke.com>
* Copyright (c) 2019 Lemonbeat GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include "gpio_gecko.h"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
soc {
flash-controller@400e0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400e0000 0x104>;
interrupts = <25 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
erase-block-size = <2048>;
};
};
usart0: usart@40010000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40010000 0x400>;
interrupts = <12 0 13 0>;
interrupt-names = "rx", "tx";
peripheral-id = <0>;
status = "disabled";
label = "USART_0";
};
usart1: usart@40010400 { /* USART1 */
compatible = "silabs,gecko-usart";
reg = <0x40010400 0x400>;
interrupts = <20 0 21 0>;
interrupt-names = "rx", "tx";
peripheral-id = <1>;
status = "disabled";
label = "USART_1";
};
usart2: usart@40010800 { /* USART2 */
compatible = "silabs,gecko-usart";
reg = <0x40010800 0x400>;
interrupts = <40 0 41 0>;
interrupt-names = "rx", "tx";
peripheral-id = <2>;
status = "disabled";
label = "USART_2";
};
usart3: usart@40010c00 { /* USART3 */
compatible = "silabs,gecko-usart";
reg = <0x40010c00 0x400>;
interrupts = <43 0 44 0>;
interrupt-names = "rx", "tx";
peripheral-id = <3>;
status = "disabled";
label = "USART_3";
};
leuart0: leuart@4004a000 { /* LEUART0 */
compatible = "silabs,gecko-leuart";
reg = <0x4004a000 0x400>;
interrupts = <22 0>;
peripheral-id = <0>;
status = "disabled";
label = "LEUART_0";
};
i2c0: i2c@4000c000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4000c000 0x400>;
interrupts = <17 0>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@4000c400 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4000c400 0x400>;
interrupts = <42 0>;
label = "I2C_1";
status = "disabled";
};
rtcc0: rtcc@40042000 {
compatible = "silabs,gecko-rtcc";
reg = <0x40042000 0x184>;
interrupts = <30 0>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
label = "RTCC_0";
};
gpio: gpio@4000a400 {
compatible = "silabs,efm32-gpio";
reg = <0x4000a400 0xf00>;
interrupts = <1 2 11 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
label = "GPIO";
ranges;
#address-cells = <1>;
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a000 0x30>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
};
gpiob: gpio@4000a030 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a030 0x30>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
};
gpioc: gpio@4000a060 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a060 0x30>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
};
gpiod: gpio@4000a090 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a090 0x30>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
};
gpioe: gpio@4000a0c0 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a0c0 0x30>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a0f0 0x30>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};