From 4d778b789a3d21ac482d4f10a36e382674e36342 Mon Sep 17 00:00:00 2001
From: Stephanos Ioannidis <root@stephanos.io>
Date: Wed, 12 Feb 2020 14:48:21 +0900
Subject: [PATCH] soc: arm: xilinx_zynqmp: Use CMSIS-Core(R)

This commit updates the `xilinx_zynqmp` SoC initialisation code to use
the CMSIS-Core(R) features.

In addition, it also defines the Core IP revision value for the SoC as
specified in the Zynq UltraScale+ Device Technical Reference Manual.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
---
 soc/arm/xilinx_zynqmp/soc.c | 10 +++++-----
 soc/arm/xilinx_zynqmp/soc.h | 10 ++--------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/arm/xilinx_zynqmp/soc.c
index 9deecdf11cc..b828e39f8a2 100644
--- a/soc/arm/xilinx_zynqmp/soc.c
+++ b/soc/arm/xilinx_zynqmp/soc.c
@@ -8,6 +8,7 @@
 #include <kernel.h>
 #include <device.h>
 #include <init.h>
+#include <arch/arm/aarch32/cortex_r/cmsis.h>
 
 /**
  *
@@ -34,9 +35,8 @@ void z_platform_init(void)
 	/*
 	 * Use normal exception vectors address range (0x0-0x1C).
 	 */
-	__asm__ volatile(
-		"mrc p15, 0, r0, c1, c0, 0;"		/* SCTLR */
-		"bic r0, r0, #" TOSTR(HIVECS) ";"	/* Clear HIVECS */
-		"mcr p15, 0, r0, c1, c0, 0;"
-		: : : "memory");
+	unsigned int sctlr = __get_SCTLR();
+
+	sctlr &= ~SCTLR_V_Msk;
+	__set_SCTLR(sctlr);
 }
diff --git a/soc/arm/xilinx_zynqmp/soc.h b/soc/arm/xilinx_zynqmp/soc.h
index 9a53a709ebb..a3765eda0af 100644
--- a/soc/arm/xilinx_zynqmp/soc.h
+++ b/soc/arm/xilinx_zynqmp/soc.h
@@ -8,13 +8,7 @@
 #ifndef _BOARD__H_
 #define _BOARD__H_
 
-#include <sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-#include <device.h>
-#include <sys/util.h>
-
-#endif /* !_ASMLANGUAGE */
+/* Define CMSIS configurations */
+#define __CR_REV		1U
 
 #endif /* _BOARD__H_ */