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soc: sensry: fix irq enable/disable

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SET/CLR registers are write-only so trying to
read/modify/write is inefficient & illegal

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit is contained in:
Benjamin Cabé 2025-06-07 21:54:39 +02:00 • committed by Benjamin Cabé
commit 4cac6583f7
1 changed files with 3 additions and 6 deletions
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9
soc/sensry/ganymed/sy1xx/common/soc.c
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@ -25,6 +25,7 @@ LOG_MODULE_REGISTER(soc);
#define SY1XX_ARCHI_ITC_ACK_SET_OFFSET 0x1c
#define SY1XX_ARCHI_ITC_ACK_CLR_OFFSET 0x20
#define SY1XX_ARCHI_ITC_FIFO_OFFSET 0x24
#define SY1XX_ARCHI_ITC_IRQ_MASK 0x1f
void sys_arch_reboot(int type)
{
@ -51,17 +52,13 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)
void soc_enable_irq(uint32_t idx)
{
uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
sys_write32(current | (1 << (idx & 0x1f)),
sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),
SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
}
void soc_disable_irq(uint32_t idx)
{
uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
sys_write32(current & (~(1 << (idx & 0x1f))),
sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),
SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
}