boards: nucleo_l412rb_p: Use dts for clocks configuration
Convert board to use of device tree for clocks configuration. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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2 changed files with 22 additions and 15 deletions
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@ -42,6 +42,27 @@
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};
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};
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};
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};
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&clk_hsi {
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <10>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(80)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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&lpuart1 {
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&lpuart1 {
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pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
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pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
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current-speed = <115200>;
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current-speed = <115200>;
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@ -2,8 +2,6 @@
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CONFIG_SOC_SERIES_STM32L4X=y
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CONFIG_SOC_SERIES_STM32L4X=y
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CONFIG_SOC_STM32L412XX=y
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CONFIG_SOC_STM32L412XX=y
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# 80MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
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# Enable MPU
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU=y
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@ -24,17 +22,5 @@ CONFIG_PINMUX=y
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# enable GPIO
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# enable GPIO
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CONFIG_GPIO=y
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CONFIG_GPIO=y
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# clock configuration
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# Enable Clocks
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
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# produce 80MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=10
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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