boards: s32z270dc2_r52: enable Ethernet support

Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>

boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi

@@ -17,4 +17,39 @@
 			input-enable;
 		};
 	};
+
+	emdio_default: emdio_default {
+		group1 {
+			pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>;
+			input-enable;
+			output-enable;
+		};
+		group2 {
+			pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>;
+			input-enable;
+			output-enable;
+			drive-open-drain;
+		};
+	};
+
+	eth0_default: eth0_default {
+		group1 {
+			pinmux = <PF2_ETH_0_RX_CLK>,
+				<PF3_ETH_0_RGMII_RXCTL>,
+				<PF4_ETH_0_RGMII_RXD_0>,
+				<PF5_ETH_0_RGMII_RXD_1>,
+				<PF6_ETH_0_RGMII_RXD_2>,
+				<PF7_ETH_0_RGMII_RXD_3>;
+			input-enable;
+		};
+		group2 {
+			pinmux = <PE12_ETH_0_RGMII_TXC>,
+				<PE13_ETH_0_RGMII_TXCTL>,
+				<PE14_ETH_0_RGMII_TXD_0>,
+				<PE15_ETH_0_RGMII_TXD_1>,
+				<PF0_ETH_0_RGMII_TXD_2>,
+				<PF1_ETH_0_RGMII_TXD_3>;
+			output-enable;
+		};
+	};
 };

boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi

@@ -89,3 +89,26 @@
 &swt4 {
 	clock-frequency = <48000000>;
 };
+
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	protocol = "clause 22";
+	status = "okay";
+
+	phy0: ethernet-phy {
+		compatible = "ethernet-phy";
+		address = <0x7>;
+		mdio = <&emdio>;
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	clock-frequency = <300000000>;
+	phy-dev = <&phy0>;
+	status = "okay";
+};

boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts

@@ -22,3 +22,13 @@
 		watchdog0 = &swt0;
 	};
 };
+
+&mru0 {
+	rx-channels = <1>;
+	status = "okay";
+};
+
+&enetc_psi0 {
+	mboxes = <&mru0 0>;
+	mbox-names = "rx";
+};

boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml

@@ -12,3 +12,4 @@ supported:
   - uart
   - gpio
   - watchdog
+  - netif:eth

boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts

@@ -22,3 +22,13 @@
 		watchdog0 = &swt0;
 	};
 };
+
+&mru4 {
+	rx-channels = <1>;
+	status = "okay";
+};
+
+&enetc_psi0 {
+	mboxes = <&mru4 0>;
+	mbox-names = "rx";
+};

boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml

@@ -12,3 +12,4 @@ supported:
   - uart
   - gpio
   - watchdog
+  - netif:eth

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -597,5 +597,66 @@
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
+
+		netc: ethernet@74000000 {
+			reg = <0x74000000 0x1000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			emdio: mdio@74b60000 {
+				compatible = "nxp,s32-netc-emdio";
+				reg = <0x74b60000 0x1c44>;
+				status = "disabled";
+			};
+
+			enetc_psi0: ethernet@74b00000 {
+				compatible = "nxp,s32-netc-psi";
+				reg = <0x74b00000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi1: ethernet@74bc0000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74bc0000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi2: ethernet@74bd0000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74bd0000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi3: ethernet@74be0000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74be0000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi4: ethernet@74bf0000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74bf0000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi5: ethernet@74c00000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74c00000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi6: ethernet@74c10000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74c10000 0x10000>;
+				status = "disabled";
+			};
+
+			enetc_vsi7: ethernet@74c20000 {
+				compatible = "nxp,s32-netc-vsi";
+				reg = <0x74c20000 0x10000>;
+				status = "disabled";
+			};
+		};
 	};
 };

soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series

@@ -29,6 +29,25 @@ config FLASH_BASE_ADDRESS
 	default 0
 endif # !XIP
 
+# Ethernet driver must init first because it initializes the
+# NETC which is needed for EMDIO functionality
+if NET_L2_ETHERNET
+
+config MDIO_INIT_PRIORITY
+	default 70
+
+config PHY_INIT_PRIORITY
+	default 80
+
+# NETC drops TCP/UDP packets with invalid checksum
+config NET_TCP_CHECKSUM
+	default n
+
+config NET_UDP_CHECKSUM
+	default n
+
+endif # NET_L2_ETHERNET
+
 source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*"
 
 endif # SOC_SERIES_S32ZE_R52