From 4a3c630f7b6abec520e2f968f5387fc97db1f2bb Mon Sep 17 00:00:00 2001 From: Manuel Arguelles Date: Tue, 29 Nov 2022 09:51:34 +0700 Subject: [PATCH] boards: s32z270dc2_r52: enable Ethernet support Introduce DT nodes for NETC complex and enable its usage for s32z270dc2_r52 boards. Using PSI0 as default networking interface and Switch Port0 as it's the only port available on this board. Signed-off-by: Manuel Arguelles --- .../s32z270dc2_r52-pinctrl.dtsi | 35 +++++++++++ boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi | 23 +++++++ .../s32z270dc2_r52/s32z270dc2_rtu0_r52.dts | 10 +++ .../s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml | 1 + .../s32z270dc2_r52/s32z270dc2_rtu1_r52.dts | 10 +++ .../s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml | 1 + dts/arm/nxp/nxp_s32z27x_r52.dtsi | 61 +++++++++++++++++++ .../nxp_s32/s32ze/Kconfig.defconfig.series | 19 ++++++ 8 files changed, 160 insertions(+) diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi index 1978bf9808a..98fd3dcbbbd 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi @@ -17,4 +17,39 @@ input-enable; }; }; + + emdio_default: emdio_default { + group1 { + pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>; + input-enable; + output-enable; + }; + group2 { + pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>; + input-enable; + output-enable; + drive-open-drain; + }; + }; + + eth0_default: eth0_default { + group1 { + pinmux = , + , + , + , + , + ; + input-enable; + }; + group2 { + pinmux = , + , + , + , + , + ; + output-enable; + }; + }; }; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi index a9d81c2da04..c9391e9a0a0 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi @@ -89,3 +89,26 @@ &swt4 { clock-frequency = <48000000>; }; + +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + protocol = "clause 22"; + status = "okay"; + + phy0: ethernet-phy { + compatible = "ethernet-phy"; + address = <0x7>; + mdio = <&emdio>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + clock-frequency = <300000000>; + phy-dev = <&phy0>; + status = "okay"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts index 67d182cc3e2..a47ede04d4a 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts @@ -22,3 +22,13 @@ watchdog0 = &swt0; }; }; + +&mru0 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru0 0>; + mbox-names = "rx"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml index 45ca0c1bc48..f82f4147174 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml @@ -12,3 +12,4 @@ supported: - uart - gpio - watchdog + - netif:eth diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts index 57d69ed42f8..d7beacd9fba 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts @@ -22,3 +22,13 @@ watchdog0 = &swt0; }; }; + +&mru4 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru4 0>; + mbox-names = "rx"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml index 3bdfde7bf92..6b1f2e5c8a1 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml @@ -12,3 +12,4 @@ supported: - uart - gpio - watchdog + - netif:eth diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index 29a3f014d6f..320fabc4f54 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -597,5 +597,66 @@ #mbox-cells = <1>; status = "disabled"; }; + + netc: ethernet@74000000 { + reg = <0x74000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + emdio: mdio@74b60000 { + compatible = "nxp,s32-netc-emdio"; + reg = <0x74b60000 0x1c44>; + status = "disabled"; + }; + + enetc_psi0: ethernet@74b00000 { + compatible = "nxp,s32-netc-psi"; + reg = <0x74b00000 0x10000>; + status = "disabled"; + }; + + enetc_vsi1: ethernet@74bc0000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74bc0000 0x10000>; + status = "disabled"; + }; + + enetc_vsi2: ethernet@74bd0000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74bd0000 0x10000>; + status = "disabled"; + }; + + enetc_vsi3: ethernet@74be0000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74be0000 0x10000>; + status = "disabled"; + }; + + enetc_vsi4: ethernet@74bf0000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74bf0000 0x10000>; + status = "disabled"; + }; + + enetc_vsi5: ethernet@74c00000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74c00000 0x10000>; + status = "disabled"; + }; + + enetc_vsi6: ethernet@74c10000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74c10000 0x10000>; + status = "disabled"; + }; + + enetc_vsi7: ethernet@74c20000 { + compatible = "nxp,s32-netc-vsi"; + reg = <0x74c20000 0x10000>; + status = "disabled"; + }; + }; }; }; diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series index 9edf94e08e1..1820bbb548d 100644 --- a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series +++ b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series @@ -29,6 +29,25 @@ config FLASH_BASE_ADDRESS default 0 endif # !XIP +# Ethernet driver must init first because it initializes the +# NETC which is needed for EMDIO functionality +if NET_L2_ETHERNET + +config MDIO_INIT_PRIORITY + default 70 + +config PHY_INIT_PRIORITY + default 80 + +# NETC drops TCP/UDP packets with invalid checksum +config NET_TCP_CHECKSUM + default n + +config NET_UDP_CHECKSUM + default n + +endif # NET_L2_ETHERNET + source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*" endif # SOC_SERIES_S32ZE_R52