pinmux: Remove the k64 pinmux driver
The k64 pinmux driver was deprecated when the more generic mcux pinmux driver was added, but it can actually just be removed because it is not a public interface. Applications should be using the public pinmux API, not the private k64 pinmux API. There was one case in the net samples that used the private API which was cleaned up in a previous patch. Change-Id: I49a6397baa57973930cb63bd2a9883b14f7ddafd Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm
Kumar Gala
parent
7682a0d7ca
commit
4973787c10
6 changed files with 0 additions and 660 deletions
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@ -49,13 +49,6 @@ config PINMUX_INIT_PRIORITY
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rule for particular boards. Don't change this value unless you
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know what you are doing.
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config PINMUX_K64
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bool "Freescale K64-based Pin multiplexer driver"
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depends on SOC_MK64F12
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default n
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help
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Enable driver for Freescale K64-based Pin multiplexer.
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source "drivers/pinmux/Kconfig.mcux"
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source "drivers/pinmux/Kconfig.stm32"
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@ -1,11 +1,6 @@
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ccflags-y +=-I$(srctree)/drivers
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# Board initialization
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ifdef CONFIG_PINMUX_K64
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obj-y += k64/pinmux.o
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obj-$(CONFIG_BOARD_FRDM_K64F) += k64/pinmux_board_frdm_k64f.o
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obj-$(CONFIG_BOARD_HEXIWEAR_K64) += k64/pinmux_board_hexiwear.o
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endif
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obj-$(CONFIG_PINMUX_MCUX) += pinmux_mcux.o
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obj-$(CONFIG_PINMUX_STM32) += stm32/pinmux_stm32.o
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obj-$(CONFIG_PINMUX_BEETLE) += beetle/pinmux_board_v2m_beetle.o
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@ -1,163 +0,0 @@
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/* pinmux.c - pin out mapping for the Freescale K64 SoC */
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/*
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* Copyright (c) 2016, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <pinmux.h>
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#include <pinmux/pinmux.h>
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#include <pinmux/k64/pinmux.h>
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/* port pin number conversion from pin ID */
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#define PIN_FROM_ID(pin_id) (pin_id % K64_PINMUX_NUM_PINS)
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#ifdef CONFIG_GPIO_K64_A
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static inline int config_port_a(mem_addr_t *addr)
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{
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*addr = PORT_K64_A_BASE_ADDR;
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return 0;
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}
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#else
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#define config_port_a(addr) -EACCES
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#endif
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#ifdef CONFIG_GPIO_K64_B
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static inline int config_port_b(mem_addr_t *addr)
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{
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*addr = PORT_K64_B_BASE_ADDR;
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return 0;
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}
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#else
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#define config_port_b(addr) -EACCES
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#endif
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#ifdef CONFIG_GPIO_K64_C
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static inline int config_port_c(mem_addr_t *addr)
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{
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*addr = PORT_K64_C_BASE_ADDR;
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return 0;
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}
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#else
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#define config_port_c(addr) -EACCES
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#endif
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#ifdef CONFIG_GPIO_K64_D
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static inline int config_port_d(mem_addr_t *addr)
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{
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*addr = PORT_K64_D_BASE_ADDR;
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return 0;
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}
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#else
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#define config_port_d(addr) -EACCES
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#endif
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#ifdef CONFIG_GPIO_K64_E
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static inline int config_port_e(mem_addr_t *addr)
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{
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*addr = PORT_K64_E_BASE_ADDR;
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return 0;
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}
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#else
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#define config_port_e(addr) -EACCES
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#endif
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static int _fsl_k64_get_port_addr(uint8_t pin_id, mem_addr_t *port_addr_ptr)
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{
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/* determine the port base address associated with the
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* pin identifier
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*/
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if (pin_id < K64_PIN_PTB0) { /* Port A pin */
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return config_port_a(port_addr_ptr);
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} else if (pin_id < K64_PIN_PTC0) { /* Port B pin */
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return config_port_b(port_addr_ptr);
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} else if (pin_id < K64_PIN_PTD0) { /* Port C pin */
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return config_port_c(port_addr_ptr);
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} else if (pin_id < K64_PIN_PTE0) { /* Port D pin */
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return config_port_d(port_addr_ptr);
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} else { /* Port E pin */
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return config_port_e(port_addr_ptr);
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}
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}
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int _fsl_k64_set_pin(uint32_t pin_id, uint32_t func)
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{
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mem_addr_t port_base_addr;
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uint8_t port_pin;
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uint32_t status;
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if (pin_id >= PINMUX_NUM_PINS) {
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return -ENOTSUP;
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}
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/* determine the pin's port register base address */
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status = _fsl_k64_get_port_addr(pin_id, &port_base_addr);
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if (status != 0) {
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return status;
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}
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/* extract the pin number within its port */
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port_pin = PIN_FROM_ID(pin_id);
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/* set pin function and control settings */
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sys_write32(func, port_base_addr + K64_PINMUX_CTRL_OFFSET(port_pin));
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return 0;
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}
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int _fsl_k64_get_pin(uint32_t pin_id, uint32_t *func)
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{
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mem_addr_t port_base_addr;
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uint8_t port_pin;
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uint32_t status;
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if (pin_id >= PINMUX_NUM_PINS) {
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return -ENOTSUP;
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}
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/* determine the pin's port register base address */
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status = _fsl_k64_get_port_addr(pin_id, &port_base_addr);
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if (status != 0) {
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return status;
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}
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/* extract the pin number within its port */
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port_pin = PIN_FROM_ID(pin_id);
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/* get pin function and control settings */
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*func = sys_read32(port_base_addr + K64_PINMUX_CTRL_OFFSET(port_pin));
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return 0;
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}
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@ -1,290 +0,0 @@
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/* pinmux.h - Freescale K64 pinmux header */
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/*
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* Copyright (c) 2016, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Header file for Freescale K64 pin multiplexing.
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*/
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#ifndef __INCLUDE_PINMUX_K64_H
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#define __INCLUDE_PINMUX_K64_H
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#define K64_PINMUX_NUM_PINS 32 /* # of I/O pins per port */
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/* Port Control Register offsets */
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#define K64_PINMUX_CTRL_OFFSET(pin) (pin * 4)
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/*
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* The following pin settings match the K64 PORT module's
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* Pin Control Register bit fields.
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*/
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/*
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* Pin interrupt configuration:
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* At reset, interrupts are disabled for all pins.
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*/
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#define K64_PINMUX_INT_MASK (0xF << 16) /* interrupt config. */
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#define K64_PINMUX_INT_DISABLE (0x0 << 16) /* disable interrupt */
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#define K64_PINMUX_INT_LOW (0x8 << 16) /* active-low interrupt */
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#define K64_PINMUX_INT_RISING (0x9 << 16) /* rising-edge interrupt */
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#define K64_PINMUX_INT_FALLING (0xA << 16) /* falling-edge interrupt */
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#define K64_PINMUX_INT_BOTH_EDGE (0xB << 16) /* either edge interrupt */
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#define K64_PINMUX_INT_HIGH (0xC << 16) /* active-high interrupt */
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/*
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* Pin function identification:
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* At reset, the setting for PTA0/1/2/3/4 is function 7;
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* the remaining pins are set to function 0.
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*/
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#define K64_PINMUX_ALT_MASK (0x7 << 8)
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#define K64_PINMUX_ALT_0 (0x0 << 8)
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#define K64_PINMUX_ALT_1 (0x1 << 8)
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#define K64_PINMUX_ALT_2 (0x2 << 8)
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#define K64_PINMUX_ALT_3 (0x3 << 8)
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#define K64_PINMUX_ALT_4 (0x4 << 8)
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#define K64_PINMUX_ALT_5 (0x5 << 8)
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#define K64_PINMUX_ALT_6 (0x6 << 8)
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#define K64_PINMUX_ALT_7 K64_PINMUX_ALT_MASK
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#define K64_PINMUX_FUNC_GPIO K64_PINMUX_ALT_1
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#define K64_PINMUX_FUNC_DISABLED K64_PINMUX_ALT_0
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#define K64_PINMUX_FUNC_ANALOG K64_PINMUX_ALT_0
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#define K64_PINMUX_FUNC_ETHERNET K64_PINMUX_ALT_4
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#define K64_PINMUX_FUNC_SPI K64_PINMUX_ALT_2
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/*
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* Pin drive strength configuration, for output:
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* At reset, the setting for PTA0/1/2/3/4/5 is high drive strength;
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* the remaining pins are set to low drive strength.
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*/
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#define K64_PINMUX_DRV_STRN_MASK (0x1 << 6) /* drive strength select */
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#define K64_PINMUX_DRV_STRN_LOW (0x0 << 6) /* low drive strength */
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#define K64_PINMUX_DRV_STRN_HIGH (0x1 << 6) /* high drive strength */
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/*
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* Pin open drain configuration, for output:
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* At reset, open drain is disabled for all pins.
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*/
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#define K64_PINMUX_OPEN_DRN_MASK (0x1 << 5) /* open drain enable */
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#define K64_PINMUX_OPEN_DRN_DISABLE (0x0 << 5) /* disable open drain */
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#define K64_PINMUX_OPEN_DRN_ENABLE (0x1 << 5) /* enable open drain */
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/*
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* Pin slew rate configuration, for output:
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* At reset, fast slew rate is set for all pins.
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*/
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#define K64_PINMUX_SLEW_RATE_MASK (0x1 << 2) /* slew rate select */
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#define K64_PINMUX_SLEW_RATE_FAST (0x0 << 2) /* fast slew rate */
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#define K64_PINMUX_SLEW_RATE_SLOW (0x1 << 2) /* slow slew rate */
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/*
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* Pin pull-up/pull-down configuration, for input:
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* At reset, the setting for PTA1/2/3/4/5 is pull-up; PTA0 is pull-down;
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* pull-up/pull-down is disabled for the remaining pins.
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*/
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#define K64_PINMUX_PULL_EN_MASK (0x1 << 1) /* pullup/pulldown enable */
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#define K64_PINMUX_PULL_DISABLE (0x0 << 1) /* disable pullup/pulldown */
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#define K64_PINMUX_PULL_ENABLE (0x1 << 1) /* enable pullup/pulldown */
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#define K64_PINMUX_PULL_SEL_MASK (0x1 << 0) /* pullup/pulldown select */
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#define K64_PINMUX_PULL_DN (0x0 << 0) /* select pulldown */
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#define K64_PINMUX_PULL_UP (0x1 << 0) /* select pullup */
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/*
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* Pin identification, by port and pin
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*/
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#define K64_PIN_PTA0 0
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#define K64_PIN_PTA1 1
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#define K64_PIN_PTA2 2
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#define K64_PIN_PTA3 3
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#define K64_PIN_PTA4 4
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#define K64_PIN_PTA5 5
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#define K64_PIN_PTA6 6
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#define K64_PIN_PTA7 7
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#define K64_PIN_PTA8 8
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#define K64_PIN_PTA9 9
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#define K64_PIN_PTA10 10
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#define K64_PIN_PTA11 11
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#define K64_PIN_PTA12 12
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#define K64_PIN_PTA13 13
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#define K64_PIN_PTA14 14
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#define K64_PIN_PTA15 15
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#define K64_PIN_PTA16 16
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#define K64_PIN_PTA17 17
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#define K64_PIN_PTA18 18
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#define K64_PIN_PTA19 19
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#define K64_PIN_PTA20 20
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#define K64_PIN_PTA21 21
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#define K64_PIN_PTA22 22
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#define K64_PIN_PTA23 23
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#define K64_PIN_PTA24 24
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#define K64_PIN_PTA25 25
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#define K64_PIN_PTA26 26
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#define K64_PIN_PTA27 27
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#define K64_PIN_PTA28 28
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#define K64_PIN_PTA29 29
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#define K64_PIN_PTA30 30
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#define K64_PIN_PTA31 31
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#define K64_PIN_PTB0 32
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#define K64_PIN_PTB1 33
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#define K64_PIN_PTB2 34
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#define K64_PIN_PTB3 35
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#define K64_PIN_PTB4 36
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#define K64_PIN_PTB5 37
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#define K64_PIN_PTB6 38
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#define K64_PIN_PTB7 39
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#define K64_PIN_PTB8 40
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#define K64_PIN_PTB9 41
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#define K64_PIN_PTB10 42
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#define K64_PIN_PTB11 43
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#define K64_PIN_PTB12 44
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#define K64_PIN_PTB13 45
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#define K64_PIN_PTB14 46
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#define K64_PIN_PTB15 47
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#define K64_PIN_PTB16 48
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#define K64_PIN_PTB17 49
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#define K64_PIN_PTB18 50
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#define K64_PIN_PTB19 51
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#define K64_PIN_PTB20 52
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#define K64_PIN_PTB21 53
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#define K64_PIN_PTB22 54
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#define K64_PIN_PTB23 55
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#define K64_PIN_PTB24 56
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#define K64_PIN_PTB25 57
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#define K64_PIN_PTB26 58
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#define K64_PIN_PTB27 59
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#define K64_PIN_PTB28 60
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#define K64_PIN_PTB29 61
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#define K64_PIN_PTB30 62
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#define K64_PIN_PTB31 63
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#define K64_PIN_PTC0 64
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#define K64_PIN_PTC1 65
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#define K64_PIN_PTC2 66
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#define K64_PIN_PTC3 67
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#define K64_PIN_PTC4 68
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#define K64_PIN_PTC5 69
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#define K64_PIN_PTC6 70
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#define K64_PIN_PTC7 71
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#define K64_PIN_PTC8 72
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#define K64_PIN_PTC9 73
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#define K64_PIN_PTC10 74
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#define K64_PIN_PTC11 75
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#define K64_PIN_PTC12 76
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#define K64_PIN_PTC13 77
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#define K64_PIN_PTC14 78
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#define K64_PIN_PTC15 79
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#define K64_PIN_PTC16 80
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#define K64_PIN_PTC17 81
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#define K64_PIN_PTC18 82
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#define K64_PIN_PTC19 83
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#define K64_PIN_PTC20 84
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#define K64_PIN_PTC21 85
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#define K64_PIN_PTC22 86
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#define K64_PIN_PTC23 87
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#define K64_PIN_PTC24 88
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#define K64_PIN_PTC25 89
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#define K64_PIN_PTC26 90
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#define K64_PIN_PTC27 91
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#define K64_PIN_PTC28 92
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#define K64_PIN_PTC29 93
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#define K64_PIN_PTC30 94
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#define K64_PIN_PTC31 95
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#define K64_PIN_PTD0 96
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#define K64_PIN_PTD1 97
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#define K64_PIN_PTD2 98
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#define K64_PIN_PTD3 99
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#define K64_PIN_PTD4 100
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#define K64_PIN_PTD5 101
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#define K64_PIN_PTD6 102
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#define K64_PIN_PTD7 103
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#define K64_PIN_PTD8 104
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#define K64_PIN_PTD9 105
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#define K64_PIN_PTD10 106
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#define K64_PIN_PTD11 107
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#define K64_PIN_PTD12 108
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#define K64_PIN_PTD13 109
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#define K64_PIN_PTD14 110
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#define K64_PIN_PTD15 111
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#define K64_PIN_PTD16 112
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#define K64_PIN_PTD17 113
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#define K64_PIN_PTD18 114
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#define K64_PIN_PTD19 115
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#define K64_PIN_PTD20 116
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#define K64_PIN_PTD21 117
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#define K64_PIN_PTD22 118
|
||||
#define K64_PIN_PTD23 119
|
||||
#define K64_PIN_PTD24 120
|
||||
#define K64_PIN_PTD25 121
|
||||
#define K64_PIN_PTD26 122
|
||||
#define K64_PIN_PTD27 123
|
||||
#define K64_PIN_PTD28 124
|
||||
#define K64_PIN_PTD29 125
|
||||
#define K64_PIN_PTD30 126
|
||||
#define K64_PIN_PTD31 127
|
||||
|
||||
#define K64_PIN_PTE0 128
|
||||
#define K64_PIN_PTE1 129
|
||||
#define K64_PIN_PTE2 130
|
||||
#define K64_PIN_PTE3 131
|
||||
#define K64_PIN_PTE4 132
|
||||
#define K64_PIN_PTE5 133
|
||||
#define K64_PIN_PTE6 134
|
||||
#define K64_PIN_PTE7 135
|
||||
#define K64_PIN_PTE8 136
|
||||
#define K64_PIN_PTE9 137
|
||||
#define K64_PIN_PTE10 138
|
||||
#define K64_PIN_PTE11 139
|
||||
#define K64_PIN_PTE12 140
|
||||
#define K64_PIN_PTE13 141
|
||||
#define K64_PIN_PTE14 142
|
||||
#define K64_PIN_PTE15 143
|
||||
#define K64_PIN_PTE16 144
|
||||
#define K64_PIN_PTE17 145
|
||||
#define K64_PIN_PTE18 146
|
||||
#define K64_PIN_PTE19 147
|
||||
#define K64_PIN_PTE20 148
|
||||
#define K64_PIN_PTE21 149
|
||||
#define K64_PIN_PTE22 150
|
||||
#define K64_PIN_PTE23 151
|
||||
#define K64_PIN_PTE24 152
|
||||
#define K64_PIN_PTE25 153
|
||||
#define K64_PIN_PTE26 154
|
||||
#define K64_PIN_PTE27 155
|
||||
#define K64_PIN_PTE28 156
|
||||
#define K64_PIN_PTE29 157
|
||||
#define K64_PIN_PTE30 158
|
||||
#define K64_PIN_PTE31 159
|
||||
|
||||
int __deprecated _fsl_k64_set_pin(uint32_t pin_id, uint32_t func);
|
||||
|
||||
int __deprecated _fsl_k64_get_pin(uint32_t pin_id, uint32_t *func);
|
||||
|
||||
|
||||
#endif /* __INCLUDE_PINMUX_K64_H */
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
/* pinmux_board_frdm_k64f.c - pin out mapping for the Freescale FRDM-K64F board */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2016 Intel Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <kernel.h>
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <sys_io.h>
|
||||
#include <pinmux.h>
|
||||
#include <pinmux/pinmux.h>
|
||||
#include <pinmux/k64/pinmux.h>
|
||||
|
||||
/*
|
||||
* I/O pin configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Alter this table to change the default Arduino pin settings on the Freescale
|
||||
* FRDM-K64F boards. Specifically, change the PINMUX_* values to represent
|
||||
* the functionality desired.
|
||||
*
|
||||
* The FRDM-K64F board routes the PTA0/1/2 pins for JTAG/SWD signals that
|
||||
* are used for the OpenSDAv2 debug interface. These pins are also routed to
|
||||
* the Arduino header pins as D8, D3 and D5, respectively.
|
||||
* Since the K64 MCU configures these pins for JTAG/SWD signaling at reset,
|
||||
* they should only be re-configured if the debug interface is not used.
|
||||
*
|
||||
*/
|
||||
static const struct pin_config mux_config[] = {
|
||||
/* pin, selected mode */
|
||||
{ K64_PIN_PTC16, K64_PINMUX_ALT_3 }, /* UART3 RX */
|
||||
{ K64_PIN_PTC17, K64_PINMUX_ALT_3 }, /* UART3 TX */
|
||||
{ K64_PIN_PTB9, K64_PINMUX_FUNC_GPIO },
|
||||
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
|
||||
{ K64_PIN_PTA1, K64_PINMUX_FUNC_GPIO },
|
||||
#endif
|
||||
{ K64_PIN_PTB23, K64_PINMUX_FUNC_GPIO },
|
||||
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
|
||||
{ K64_PIN_PTA2, K64_PINMUX_FUNC_GPIO },
|
||||
#endif
|
||||
{ K64_PIN_PTC2, K64_PINMUX_FUNC_GPIO },
|
||||
{ K64_PIN_PTC3, K64_PINMUX_FUNC_GPIO },
|
||||
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
|
||||
{ K64_PIN_PTA0, K64_PINMUX_FUNC_GPIO },
|
||||
#endif
|
||||
{ K64_PIN_PTC4, K64_PINMUX_FUNC_GPIO },
|
||||
|
||||
{ K64_PIN_PTC6, K64_PINMUX_FUNC_GPIO }, /* SW2 / FXOS8700 INT1 */
|
||||
{ K64_PIN_PTA4, K64_PINMUX_FUNC_GPIO }, /* SW3 */
|
||||
|
||||
{ K64_PIN_PTB22, K64_PINMUX_FUNC_GPIO }, /* Red LED */
|
||||
{ K64_PIN_PTE26, K64_PINMUX_FUNC_GPIO }, /* Green LED */
|
||||
{ K64_PIN_PTB21, K64_PINMUX_FUNC_GPIO }, /* Blue LED */
|
||||
|
||||
/* SPI 0 */
|
||||
#ifdef CONFIG_SPI_0
|
||||
{ K64_PIN_PTD0, K64_PINMUX_FUNC_SPI },
|
||||
{ K64_PIN_PTD2, K64_PINMUX_FUNC_SPI },
|
||||
{ K64_PIN_PTD3, K64_PINMUX_FUNC_SPI },
|
||||
{ K64_PIN_PTD1, K64_PINMUX_FUNC_SPI },
|
||||
#else
|
||||
{ K64_PIN_PTD0, K64_PINMUX_FUNC_GPIO },
|
||||
{ K64_PIN_PTD2, K64_PINMUX_FUNC_GPIO },
|
||||
{ K64_PIN_PTD3, K64_PINMUX_FUNC_GPIO },
|
||||
{ K64_PIN_PTD1, K64_PINMUX_FUNC_GPIO },
|
||||
#endif
|
||||
|
||||
/* I2C0_SDA */
|
||||
{ K64_PIN_PTE25, (K64_PINMUX_ALT_5 | K64_PINMUX_OPEN_DRN_ENABLE) },
|
||||
/* I2C0_SCL */
|
||||
{ K64_PIN_PTE24, (K64_PINMUX_ALT_5 | K64_PINMUX_OPEN_DRN_ENABLE) },
|
||||
{ K64_PIN_PTB2, K64_PINMUX_FUNC_ANALOG }, /* ADC0_SE12/Analog In 0 */
|
||||
{ K64_PIN_PTB3, K64_PINMUX_FUNC_ANALOG }, /* ADC0_SE13/Analog In 1 */
|
||||
{ K64_PIN_PTB10, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE14/Analog In 2 */
|
||||
{ K64_PIN_PTB11, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE15/Analog In 3 */
|
||||
{ K64_PIN_PTC11, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE7b/Analog In 4 */
|
||||
{ K64_PIN_PTC10, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE6b/Analog In 5 */
|
||||
|
||||
#if CONFIG_ETH_MCUX_0
|
||||
{ K64_PIN_PTA5, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA12, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA13, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA14, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA15, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA16, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA17, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTA28, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTB0, (K64_PINMUX_FUNC_ETHERNET |
|
||||
K64_PINMUX_OPEN_DRN_ENABLE |
|
||||
K64_PINMUX_PULL_ENABLE |
|
||||
K64_PINMUX_PULL_UP)},
|
||||
{ K64_PIN_PTB1, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTC16, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTC17, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTC18, K64_PINMUX_FUNC_ETHERNET},
|
||||
{ K64_PIN_PTC19, K64_PINMUX_FUNC_ETHERNET},
|
||||
#endif
|
||||
};
|
||||
|
||||
static int fsl_frdm_k64f_pin_init(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
/* configure the pins from the default mapping above */
|
||||
for (int i = 0; i < ARRAY_SIZE(mux_config); i++) {
|
||||
_fsl_k64_set_pin(mux_config[i].pin_num, mux_config[i].mode);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(fsl_frdm_k64f_pin_init, POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY);
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
/* pinmux_board_hexiwear.c - pin out mapping for the NXP Hexiwear board */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2016 Intel Corporation
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <kernel.h>
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <sys_io.h>
|
||||
#include <pinmux.h>
|
||||
#include <pinmux/pinmux.h>
|
||||
#include <pinmux/k64/pinmux.h>
|
||||
|
||||
/*
|
||||
* I/O pin configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Alter this table to change the default pin settings on the NXP Hexiwear
|
||||
* boards. Specifically, change the PINMUX_* values to represent the
|
||||
* functionality desired.
|
||||
*/
|
||||
static const struct pin_config mux_config[] = {
|
||||
/* pin, selected mode */
|
||||
|
||||
/* RGB */
|
||||
{ K64_PIN_PTC8, K64_PINMUX_FUNC_GPIO},
|
||||
{ K64_PIN_PTC9, K64_PINMUX_FUNC_GPIO},
|
||||
{ K64_PIN_PTD0, K64_PINMUX_FUNC_GPIO},
|
||||
|
||||
/* I2C1 - accel/mag, gyro, pressure */
|
||||
{ K64_PIN_PTC10, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
|
||||
{ K64_PIN_PTC11, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
|
||||
|
||||
/* FXOS8700 INT1 */
|
||||
{ K64_PIN_PTC1, K64_PINMUX_FUNC_GPIO},
|
||||
|
||||
/* UART4 - BLE */
|
||||
{ K64_PIN_PTE25, K64_PINMUX_ALT_3 },
|
||||
{ K64_PIN_PTE24, K64_PINMUX_ALT_3 },
|
||||
};
|
||||
|
||||
static int hexiwear_pin_init(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
/* configure the pins from the default mapping above */
|
||||
for (int i = 0; i < ARRAY_SIZE(mux_config); i++) {
|
||||
_fsl_k64_set_pin(mux_config[i].pin_num, mux_config[i].mode);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(hexiwear_pin_init, POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY);
|
||||
Loading…
Add table
Add a link
Reference in a new issue