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intc: intc_cavs: Use DTS labels for device names

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Replace Kconfig device names with one's that come from device tree like
most all other devices do.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-20 10:29:32 -05:00 • committed by Kumar Gala
commit 492fbf7bba
7 changed files with 78 additions and 80 deletions
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16
drivers/interrupt_controller/Kconfig.cavs
View file

@ -18,34 +18,18 @@ config CAVS_ISR_TBL_OFFSET
This indicates the offset in the SW_ISR_TABLE beginning from where This indicates the offset in the SW_ISR_TABLE beginning from where
the ISRs for CAVS Interrupt Controller are assigned. the ISRs for CAVS Interrupt Controller are assigned.
config CAVS_ICTL_0_NAME
string "CAVS 0 Driver name"
default "CAVS_0"
config CAVS_ICTL_0_OFFSET config CAVS_ICTL_0_OFFSET
int "Parent interrupt number to which CAVS_0 maps" int "Parent interrupt number to which CAVS_0 maps"
default 0 default 0
config CAVS_ICTL_1_NAME
string "CAVS 1 Driver name"
default "CAVS_1"
config CAVS_ICTL_1_OFFSET config CAVS_ICTL_1_OFFSET
int "Parent interrupt number to which CAVS_1 maps" int "Parent interrupt number to which CAVS_1 maps"
default 0 default 0
config CAVS_ICTL_2_NAME
string "CAVS 2 Driver name"
default "CAVS_2"
config CAVS_ICTL_2_OFFSET config CAVS_ICTL_2_OFFSET
int "Parent interrupt number to which CAVS_2 maps" int "Parent interrupt number to which CAVS_2 maps"
default 0 default 0
config CAVS_ICTL_3_NAME
string "CAVS 3 Driver name"
default "CAVS_3"
config CAVS_ICTL_3_OFFSET config CAVS_ICTL_3_OFFSET
int "Parent interrupt number to which CAVS_3 maps" int "Parent interrupt number to which CAVS_3 maps"
default 0 default 0

8
drivers/interrupt_controller/intc_cavs.c
View file

@ -136,7 +136,7 @@ static struct cavs_ictl_runtime cavs_0_runtime = {
.base_addr = DT_CAVS_ICTL_BASE_ADDR, .base_addr = DT_CAVS_ICTL_BASE_ADDR,
}; };
DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME, DEVICE_AND_API_INIT(cavs_ictl_0, DT_LABEL(DT_NODELABEL(cavs0)),
cavs_ictl_0_initialize, &cavs_0_runtime, &cavs_config_0, cavs_ictl_0_initialize, &cavs_0_runtime, &cavs_config_0,
PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis); PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
@ -164,7 +164,7 @@ static struct cavs_ictl_runtime cavs_1_runtime = {
.base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers), .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers),
}; };
DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME, DEVICE_AND_API_INIT(cavs_ictl_1, DT_LABEL(DT_NODELABEL(cavs1)),
cavs_ictl_1_initialize, &cavs_1_runtime, &cavs_config_1, cavs_ictl_1_initialize, &cavs_1_runtime, &cavs_config_1,
PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis); PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
@ -192,7 +192,7 @@ static struct cavs_ictl_runtime cavs_2_runtime = {
.base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2, .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2,
}; };
DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME, DEVICE_AND_API_INIT(cavs_ictl_2, DT_LABEL(DT_NODELABEL(cavs2)),
cavs_ictl_2_initialize, &cavs_2_runtime, &cavs_config_2, cavs_ictl_2_initialize, &cavs_2_runtime, &cavs_config_2,
PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis); PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
@ -220,7 +220,7 @@ static struct cavs_ictl_runtime cavs_3_runtime = {
.base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3, .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3,
}; };
DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME, DEVICE_AND_API_INIT(cavs_ictl_3, DT_LABEL(DT_NODELABEL(cavs3)),
cavs_ictl_3_initialize, &cavs_3_runtime, &cavs_config_3, cavs_ictl_3_initialize, &cavs_3_runtime, &cavs_config_3,
PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis); PRE_KERNEL_1, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);

3
dts/bindings/interrupt-controller/intel,cavs-intc.yaml
View file

@ -11,6 +11,9 @@ properties:
interrupts: interrupts:
required: true required: true
label:
required: true
"#interrupt-cells": "#interrupt-cells":
const: 3 const: 3

4
dts/xtensa/intel/intel_apl_adsp.dtsi
View file

@ -53,6 +53,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <6 0 0>; interrupts = <6 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_0";
}; };
cavs1: cavs@1610 { cavs1: cavs@1610 {
@ -62,6 +63,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0xA 0 0>; interrupts = <0xA 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_1";
}; };
cavs2: cavs@1620 { cavs2: cavs@1620 {
@ -71,6 +73,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0XD 0 0>; interrupts = <0XD 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_2";
}; };
cavs3: cavs@1630 { cavs3: cavs@1630 {
@ -80,6 +83,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0x10 0 0>; interrupts = <0x10 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_3";
}; };
idc: idc@1200 { idc: idc@1200 {

4
dts/xtensa/intel/intel_s1000.dtsi
View file

@ -58,6 +58,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <6 0 0>; interrupts = <6 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_0";
}; };
cavs1: cavs@78810 { cavs1: cavs@78810 {
@ -67,6 +68,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0xA 0 0>; interrupts = <0xA 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_1";
}; };
cavs2: cavs@78820 { cavs2: cavs@78820 {
@ -76,6 +78,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0XD 0 0>; interrupts = <0XD 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_2";
}; };
cavs3: cavs@78830 { cavs3: cavs@78830 {
@ -85,6 +88,7 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <0x10 0 0>; interrupts = <0x10 0 0>;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
label = "CAVS_3";
}; };
idc: idc@1200 { idc: idc@1200 {

73
soc/xtensa/intel_apl_adsp/soc.c
View file

@ -21,22 +21,24 @@
#include <logging/log.h> #include <logging/log.h>
LOG_MODULE_REGISTER(soc); LOG_MODULE_REGISTER(soc);
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
void z_soc_irq_enable(u32_t irq) void z_soc_irq_enable(u32_t irq)
{ {
struct device *dev_cavs; struct device *dev_cavs;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
@ -64,17 +66,17 @@ void z_soc_irq_disable(u32_t irq)
struct device *dev_cavs; struct device *dev_cavs;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
@ -105,17 +107,17 @@ int z_soc_irq_is_enabled(unsigned int irq)
int ret = 0; int ret = 0;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
@ -142,7 +144,7 @@ int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
void *parameter, u32_t flags) void *parameter, u32_t flags)
{ {
uint32_t table_idx; uint32_t table_idx;
uint32_t cavs_irq; uint32_t cavs_irq, cavs_idx;
int ret; int ret;
ARG_UNUSED(flags); ARG_UNUSED(flags);
@ -160,26 +162,25 @@ int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
/* Figure out the base index. */ /* Figure out the base index. */
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET; cavs_idx = 0;
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET + cavs_idx = 1;
CONFIG_MAX_IRQ_PER_AGGREGATOR;
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET + cavs_idx = 2;
CONFIG_MAX_IRQ_PER_AGGREGATOR * 2;
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET + cavs_idx = 3;
CONFIG_MAX_IRQ_PER_AGGREGATOR * 3;
break; break;
default: default:
ret = -EINVAL; ret = -EINVAL;
goto irq_connect_out; goto irq_connect_out;
} }
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET +
CONFIG_MAX_IRQ_PER_AGGREGATOR * cavs_idx;
table_idx += cavs_irq; table_idx += cavs_irq;
_sw_isr_table[table_idx].arg = parameter; _sw_isr_table[table_idx].arg = parameter;

50
soc/xtensa/intel_s1000/soc.c
View file

@ -19,22 +19,24 @@ LOG_MODULE_REGISTER(soc);
static u32_t ref_clk_freq; static u32_t ref_clk_freq;
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
void z_soc_irq_enable(u32_t irq) void z_soc_irq_enable(u32_t irq)
{ {
struct device *dev_cavs, *dev_ictl; struct device *dev_cavs, *dev_ictl;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
@ -83,17 +85,17 @@ void z_soc_irq_disable(u32_t irq)
struct device *dev_cavs, *dev_ictl; struct device *dev_cavs, *dev_ictl;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
@ -153,17 +155,17 @@ int z_soc_irq_is_enabled(unsigned int irq)
int ret = -EINVAL; int ret = -EINVAL;
switch (XTENSA_IRQ_NUMBER(irq)) { switch (XTENSA_IRQ_NUMBER(irq)) {
case DT_CAVS_ICTL_0_IRQ: case DT_IRQN(CAVS_INTC_NODE(0)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
break; break;
case DT_CAVS_ICTL_1_IRQ: case DT_IRQN(CAVS_INTC_NODE(1)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
break; break;
case DT_CAVS_ICTL_2_IRQ: case DT_IRQN(CAVS_INTC_NODE(2)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
break; break;
case DT_CAVS_ICTL_3_IRQ: case DT_IRQN(CAVS_INTC_NODE(3)):
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */