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soc: it8xxx2: enable CONFIG_RISCV_GP

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This will bring better performance on accessing global variables
that are in 4K span by the GP register.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-10-05 17:11:14 +08:00 • committed by Anas Nashif
commit 48e0dbbca4
2 changed files with 11 additions and 0 deletions
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8
soc/riscv/riscv-ite/common/vector.S
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@ -16,6 +16,14 @@ GTEXT(__initialize)
GTEXT(__irq_wrapper) GTEXT(__irq_wrapper)
SECTION_FUNC(vectors, __start) SECTION_FUNC(vectors, __start)
#ifdef CONFIG_RISCV_GP
.option push
.option norelax
/* Configure the GP register */
la gp, __global_pointer$
.option pop
#endif
.option norvc; .option norvc;
/* /*

3
soc/riscv/riscv-ite/it8xxx2/Kconfig.defconfig.series
View file

@ -13,6 +13,9 @@ config ITE_IT8XXX2_INTC
select FLASH_HAS_DRIVER_ENABLED select FLASH_HAS_DRIVER_ENABLED
select HAS_FLASH_LOAD_OFFSET select HAS_FLASH_LOAD_OFFSET
config RISCV_GP
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 default 32768