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drivers: can: stm32fd: rename CONFIG_CAN_STM32_CLOCK_DIVISOR

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Rename CONFIG_CAN_STM32_CLOCK_DIVISOR to
CONFIG_CAN_STM32FD_CLOCK_DIVISOR to match driver Kconfig name.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen 2022-04-20 15:14:58 +02:00 • committed by Carles Cufí
commit 45d4909024
2 changed files with 14 additions and 8 deletions
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5
drivers/can/Kconfig.stm32fd
View file

@ -52,8 +52,9 @@ config CAN_STM32FD_CLOCK_SOURCE_PCLK1
endchoice endchoice
config CAN_STM32_CLOCK_DIVISOR config CAN_STM32FD_CLOCK_DIVISOR
int "CAN clock divisor" int "CAN clock divisor"
depends on CAN_STM32FD_CLOCK_SOURCE_PCLK1
range 1 30 range 1 30
default 1 default 1
help help
@ -62,4 +63,4 @@ config CAN_STM32_CLOCK_DIVISOR
Note that the the divisor affects all CAN controllers. Note that the the divisor affects all CAN controllers.
Allowed values: 1 or 2 * n, where n <= 15. Allowed values: 1 or 2 * n, where n <= 15.
endif #CAN_STM32FD endif # CAN_STM32FD

17
drivers/can/can_stm32fd.c
View file

@ -26,10 +26,15 @@ LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
#error "Unsupported FDCAN clock source" #error "Unsupported FDCAN clock source"
#endif #endif
#if CONFIG_CAN_STM32_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32_CLOCK_DIVISOR & 0x01 #ifdef CONFIG_CAN_STM32FD_CLOCK_DIVISOR
#error CAN_STM32_CLOCK_DIVISOR invalid.\ #if CONFIG_CAN_STM32FD_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32FD_CLOCK_DIVISOR & 0x01
Allowed values are 1 or 2 * n, where n <= 15 #error CAN_STM32FD_CLOCK_DIVISOR invalid. Allowed values are 1 or 2 * n, where n <= 15.
#endif #else
#define CAN_STM32FD_CLOCK_DIVISOR CONFIG_CAN_STM32FD_CLOCK_DIVISOR
#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR */
#else
#define CAN_STM32FD_CLOCK_DIVISOR 1U
#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR*/
#define DT_DRV_COMPAT st_stm32_fdcan #define DT_DRV_COMPAT st_stm32_fdcan
@ -43,7 +48,7 @@ static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
return -EIO; return -EIO;
} }
*rate = rate_tmp / CONFIG_CAN_STM32_CLOCK_DIVISOR; *rate = rate_tmp / CAN_STM32FD_CLOCK_DIVISOR;
return 0; return 0;
} }
@ -53,7 +58,7 @@ static void can_stm32fd_clock_enable(void)
LL_RCC_SetFDCANClockSource(CAN_STM32FD_CLOCK_SOURCE); LL_RCC_SetFDCANClockSource(CAN_STM32FD_CLOCK_SOURCE);
__HAL_RCC_FDCAN_CLK_ENABLE(); __HAL_RCC_FDCAN_CLK_ENABLE();
FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1; FDCAN_CONFIG->CKDIV = CAN_STM32FD_CLOCK_DIVISOR >> 1;
} }
static void can_stm32fd_set_state_change_callback(const struct device *dev, static void can_stm32fd_set_state_change_callback(const struct device *dev,