boards: st: add stm32h533re board support
Add board support for stm32h533re Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
This commit is contained in:
IBEN EL HADJ MESSAOUD Marwa
David Leach
parent
413eb8ad1d
commit
44a5198a99
10 changed files with 600 additions and 0 deletions
5
boards/st/nucleo_h533re/Kconfig.nucleo_h533re
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boards/st/nucleo_h533re/Kconfig.nucleo_h533re
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NUCLEO_H533RE
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select SOC_STM32H533XX
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38
boards/st/nucleo_h533re/arduino_r3_connector.dtsi
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boards/st/nucleo_h533re/arduino_r3_connector.dtsi
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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arduino_header: connector {
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compatible = "arduino-header-r3";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpioa 0 0>, /* A0 */
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<1 0 &gpioa 1 0>, /* A1 */
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<2 0 &gpiob 1 0>, /* A2 */
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<3 0 &gpiob 0 0>, /* A3 */
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<4 0 &gpioc 1 0>, /* A4 */
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<5 0 &gpioc 0 0>, /* A5 */
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<6 0 &gpiob 15 0>, /* D0 */
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<7 0 &gpiob 14 0>, /* D1 */
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<8 0 &gpioc 8 0>, /* D2 */
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<9 0 &gpiob 3 0>, /* D3 */
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<10 0 &gpiob 5 0>, /* D4 */
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<11 0 &gpiob 4 0>, /* D5 */
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<12 0 &gpiob 10 0>, /* D6 */
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<13 0 &gpioa 8 0>, /* D7 */
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<14 0 &gpioc 7 0>, /* D8 */
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<15 0 &gpioc 6 0>, /* D9 */
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<16 0 &gpioc 9 0>, /* D10 */
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<17 0 &gpioa 7 0>, /* D11 */
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<18 0 &gpioa 6 0>, /* D12 */
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<19 0 &gpioa 5 0>, /* D13 */
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<20 0 &gpiob 7 0>, /* D14 */
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<21 0 &gpiob 6 0>; /* D15 */
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};
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};
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arduino_serial: &usart1 {};
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11
boards/st/nucleo_h533re/board.cmake
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boards/st/nucleo_h533re/board.cmake
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset-mode=hw")
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board_runner_args(pyocd "--target=stm32h533retx")
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board_runner_args(jlink "--device=STM32H533RE" "--reset-after-load")
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include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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boards/st/nucleo_h533re/board.yml
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boards/st/nucleo_h533re/board.yml
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board:
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name: nucleo_h533re
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vendor: st
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socs:
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- name: stm32h533xx
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BIN
boards/st/nucleo_h533re/doc/img/nucleo_h533re.jpg
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boards/st/nucleo_h533re/doc/img/nucleo_h533re.jpg
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Binary file not shown.
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After Width: | Height: | Size: 88 KiB |
306
boards/st/nucleo_h533re/doc/index.rst
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boards/st/nucleo_h533re/doc/index.rst
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.. _nucleo_h533re_board:
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ST Nucleo H533RE
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################
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Overview
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********
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The Nucleo H533RE board is designed as an affordable development platform for
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STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H533RET6
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microcontroller with TrustZone |reg|.
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Here are some highlights of the Nucleo H533RE board:
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- STM32H533RE microcontroller featuring 512 kbytes of Flash memory and 272 Kbytes of
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SRAM in LQFP64 package
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- Board connectors:
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- USB Type-C |trade| Sink device FS
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- ST Zio expansion connector including Arduino Uno V3 connectivity (CN5, CN6, CN8, CN9)
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- ST morpho extension connector (CN7, CN10)
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- Flexible board power supply:
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- 5V_USB_STLK from ST-Link USB connector
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- VIN (7 - 12V, 0.8) supplied via pin header CN6 pin 8 or CN7 pin 24
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- ESV on the ST morpho connector CN7 Pin 6 (5V, O.5A)
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- VBUS_STLK from a USB charger via the ST-LINK USB connector
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- VBUSC from the USB user connector (5V, 0.5A)
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- 3V3_EXT supplied via a pin header CN6 pin 4 or CN7 pin 16 (3.3V, 1.3A)
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- On-board ST-LINK/V3EC debugger/programmer
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- mass storage
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- Virtual COM port
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- debug port
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- One user LED shared with ARDUINO |reg| Uno V3
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- Two push-buttons: USER and RESET
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- 32.768 kHz crystal oscillator
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More information about the board can be found at the `NUCLEO_H533RE website`_.
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.. image:: img/nucleo_h533re.jpg
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:align: center
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:alt: NUCLEO H533RE
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Hardware
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********
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The STM32H533xx devices are high-performance microcontrollers from the STM32H5
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Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core.
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They operate at a frequency of up to 250 MHz.
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- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
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- Performance benchmark:
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- 375 DMPIS/MHz (Dhrystone 2.1)
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- Security
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- Arm |reg| TrustZone |reg| with Armv8-M mainline security extension
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- Up to eight configurable SAU regions
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- TrustZone |reg| aware and securable peripherals
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- Flexible life cycle scheme with secure debug authentication
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- SESIP3 and PSA Level 3 certified assurance target
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- Preconfigured immutable root of trust (ST-iROT)
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- SFI (secure firmware installation)
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- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
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- Secure data storage with hardware unique key (HUK)
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- Secure firmware upgrade support with TF-M
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- Two AES coprocessors including one with DPA resistance
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- Public key accelerator, DPA resistant
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- On-the-fly decryption of Octo-SPI external memories
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- HASH hardware accelerator
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- True random number generator, NIST SP800-90B compliant
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- 96-bit unique ID
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- Active tampers
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- Clock management:
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- 24 MHz crystal oscillator (HSE)
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- 32 kHz crystal oscillator for RTC (LSE)
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- Internal 64 MHz (HSI) trimmable by software
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- Internal low-power 32 kHz RC (LSI)( |plusminus| 5%)
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- Internal 4 MHz oscillator (CSI), trimmable by software
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- Internal 48 MHz (HSI48) with recovery system
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- 3 PLLs for system clock, USB, audio, ADC
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- Power management
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- Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
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- Embedded SMPS step-down converter
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- RTC with HW calendar, alarms and calibration
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- Up to 112 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V
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- Up to 16 timers and 2 watchdogs
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- 8x 16-bit
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- 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
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- 2x 16-bit low-power 16-bit timers (available in Stop mode)
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- 2x watchdogs
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- 2x SysTick timer
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- Memories
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- Up to 512 Kbytes Flash, 2 banks read-while-write
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- 1 Kbyte OTP (one-time programmable)
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- 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)
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- 2 Kbytes of backup SRAM available in the lowest power modes
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- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories
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- 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
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- 1x SD/SDIO/MMC interfaces
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- Rich analog peripherals (independent supply)
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- 2x 12-bit ADC with up to 5 MSPS in 12-bit
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- 1x 12-bit DAC with 2 channels
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- 1x Digital temperature sensor
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- Voltage reference buffer
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- 34x communication interfaces
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- 1x USB Type-C / USB power-delivery controller
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- 1x USB 2.0 full-speed host and device (crystal-less)
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- 3x I2C FM+ interfaces (SMBus/PMBus)
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- 2x I3C interface
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- 6x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)
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- 1x LP UART
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- 4x SPIs including 3 muxed with full-duplex I2S
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- 4x additional SPI from 4x USART when configured in Synchronous mode
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- 2x FDCAN
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- 1x SDMMC interface
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- 2x 16 channel DMA controllers
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- 1x 8- to 14- bit camera interface
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- 1x HDMI-CEC
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- 1x 16-bit parallel slave synchronous-interface
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- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
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More information about STM32H533RE can be found here:
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- `STM32H533re on www.st.com`_
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- `STM32H533 reference manual`_
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Supported Features
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==================
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The Zephyr nucleo_h533re board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| CLOCK | on-chip | reset and clock control |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| PWM | on-chip | PWM |
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+-----------+------------+-------------------------------------+
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| RNG | on-chip | True Random number generator |
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+-----------+------------+-------------------------------------+
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| RTC | on-chip | Real Time Clock |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | independent watchdog |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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The default configuration can be found in the defconfig and dts files:
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- Secure target:
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- :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re_defconfig`
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- :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re.dts`
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Zephyr board options
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====================
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The STM32H533 is a SoC with Cortex-M33 architecture. Zephyr provides support
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for building for Secure firmware.
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The BOARD options are summarized below:
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+----------------------+-----------------------------------------------+
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| BOARD | Description |
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+======================+===============================================+
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| nucleo_h533re | For building Secure firmware |
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+----------------------+-----------------------------------------------+
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Connections and IOs
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===================
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Nucleo H533RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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For more details please refer to `STM32H5 Nucleo-64 board User Manual`_.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- ADC1 channel 14 input: PB1
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- USART1 TX/RX : PB14/PB15 (Arduino USART1)
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- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9
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- UART2 TX/RX : PA2/PA3 (VCP)
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- USER_PB : PC13
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System Clock
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------------
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Nucleo H533RE System Clock could be driven by internal or external oscillator,
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as well as main PLL clock. By default System clock is driven by PLL clock at
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240MHz, driven by an 24MHz high-speed external clock.
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Serial Port
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-----------
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Nucleo H533RE board has up to 6 U(S)ARTs. The Zephyr console output is assigned
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to USART2. Default settings are 115200 8N1.
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Programming and Debugging
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*************************
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Applications for the ``nucleo_h533re`` board can be built and
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flashed in the usual way (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Flashing
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========
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Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface.
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This probe allows to flash the board using various tools.
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Board is configured to be flashed using west STM32CubeProgrammer runner.
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Installation of `STM32CubeProgrammer`_ is then required to flash the board.
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Alternatively, pyocd or jlink via an external probe can also be used to flash
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and debug the board if west is told to use it as runner, which can be done by
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passing either or ``-r pyocd``, or ``-r jlink``.
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For pyocd additional target information needs to be installed.
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This can be done by executing the following commands.
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.. code-block:: console
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$ pyocd pack --update
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$ pyocd pack --install stm32h5
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Flashing an application to Nucleo H533RE
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------------------------------------------
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Connect the Nucleo H533RE to your host computer using the USB port.
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Then build and flash an application. Here is an example for the
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:ref:`hello_world` application.
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Run a serial host program to connect with your Nucleo board:
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.. code-block:: console
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$ minicom -D /dev/ttyACM0
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Then build and flash the application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: nucleo_h533re
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:goals: build flash
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You should see the following message on the console:
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.. code-block:: console
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Hello World! nucleo_h533re
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Debugging
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=========
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You can debug an application in the usual way. Here is an example for the
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:zephyr:code-sample:`blinky` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/basic/blinky
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:board: nucleo_h533re
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:goals: debug
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.. _NUCLEO_H533RE website:
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https://www.st.com/en/evaluation-tools/nucleo-h533re
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|
.. _STM32H5 Nucleo-64 board User Manual:
|
||||||
|
https://www.st.com/resource/en/user_manual/um3121-stm32h5-nucleo64-board-mb1814-stmicroelectronics.pdf
|
||||||
|
|
||||||
|
.. _STM32H533RE on www.st.com:
|
||||||
|
https://www.st.com/en/microcontrollers-microprocessors/stm32h533re
|
||||||
|
|
||||||
|
.. _STM32H533 reference manual:
|
||||||
|
https://www.st.com/resource/en/reference_manual/rm0481-stm32h533-stm32h563-stm32h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||||
|
|
||||||
|
.. _STM32CubeProgrammer:
|
||||||
|
https://www.st.com/en/development-tools/stm32cubeprog.html
|
||||||
137
boards/st/nucleo_h533re/nucleo_h533re.dts
Normal file
137
boards/st/nucleo_h533re/nucleo_h533re.dts
Normal file
|
|
@ -0,0 +1,137 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 STMicroelectronics
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include <st/h5/stm32h533Xe.dtsi>
|
||||||
|
#include <st/h5/stm32h533retx-pinctrl.dtsi>
|
||||||
|
#include "arduino_r3_connector.dtsi"
|
||||||
|
#include "st_morpho_connector.dtsi"
|
||||||
|
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32H533RE-NUCLEO board";
|
||||||
|
compatible = "st,stm32h533re-nucleo";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
zephyr,console = &usart2;
|
||||||
|
zephyr,shell-uart = &usart2;
|
||||||
|
zephyr,sram = &sram1;
|
||||||
|
zephyr,flash = &flash0;
|
||||||
|
};
|
||||||
|
|
||||||
|
leds: leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
green_led_2: led_42 {
|
||||||
|
gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
|
||||||
|
label = "User LD2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
pwmleds {
|
||||||
|
compatible = "pwm-leds";
|
||||||
|
|
||||||
|
green_pwm_led: green_pwm_led {
|
||||||
|
pwms = <&pwm3 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
user_button: button {
|
||||||
|
label = "User";
|
||||||
|
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
|
||||||
|
zephyr,code = <INPUT_KEY_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
led0 = &green_led_2;
|
||||||
|
pwm-led0 = &green_pwm_led;
|
||||||
|
sw0 = &user_button;
|
||||||
|
watchdog0 = &iwdg;
|
||||||
|
volt-sensor0 = &vref;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&clk_csi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&clk_hsi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&clk_hse {
|
||||||
|
clock-frequency = <DT_FREQ_M(24)>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pll {
|
||||||
|
div-m = <2>;
|
||||||
|
mul-n = <40>;
|
||||||
|
div-p = <2>;
|
||||||
|
div-q = <2>;
|
||||||
|
div-r = <2>;
|
||||||
|
clocks = <&clk_hse>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
clocks = <&pll>;
|
||||||
|
clock-frequency = <DT_FREQ_M(240)>;
|
||||||
|
ahb-prescaler = <1>;
|
||||||
|
apb1-prescaler = <1>;
|
||||||
|
apb2-prescaler = <1>;
|
||||||
|
apb3-prescaler = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usart1 {
|
||||||
|
pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
current-speed = <115200>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usart2 {
|
||||||
|
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
current-speed = <115200>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&timers3 {
|
||||||
|
st,prescaler = <1000>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
pwm3: pwm {
|
||||||
|
pinctrl-0 = <&tim3_ch3_pb0>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&vref {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&clk_lse {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
|
||||||
|
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
17
boards/st/nucleo_h533re/nucleo_h533re.yaml
Normal file
17
boards/st/nucleo_h533re/nucleo_h533re.yaml
Normal file
|
|
@ -0,0 +1,17 @@
|
||||||
|
# Copyright (c) 2024
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
identifier: nucleo_h533re
|
||||||
|
name: ST Nucleo H533RE
|
||||||
|
type: mcu
|
||||||
|
arch: arm
|
||||||
|
toolchain:
|
||||||
|
- zephyr
|
||||||
|
ram: 272
|
||||||
|
flash: 512
|
||||||
|
supported:
|
||||||
|
- gpio
|
||||||
|
- watchdog
|
||||||
|
- pwm
|
||||||
|
- rtc
|
||||||
|
vendor: st
|
||||||
16
boards/st/nucleo_h533re/nucleo_h533re_defconfig
Normal file
16
boards/st/nucleo_h533re/nucleo_h533re_defconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
# enable uart driver
|
||||||
|
CONFIG_SERIAL=y
|
||||||
|
|
||||||
|
# console
|
||||||
|
CONFIG_CONSOLE=y
|
||||||
|
CONFIG_UART_CONSOLE=y
|
||||||
|
|
||||||
|
# Enable clock
|
||||||
|
CONFIG_CLOCK_CONTROL=y
|
||||||
|
|
||||||
|
# enable GPIO
|
||||||
|
CONFIG_GPIO=y
|
||||||
|
# enable pin controller
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
65
boards/st/nucleo_h533re/st_morpho_connector.dtsi
Normal file
65
boards/st/nucleo_h533re/st_morpho_connector.dtsi
Normal file
|
|
@ -0,0 +1,65 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 STMicroelectronics
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||||
|
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
st_morpho_header: st-morpho-header {
|
||||||
|
compatible = "st-morpho-header";
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
|
||||||
|
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
|
||||||
|
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
|
||||||
|
<ST_MORPHO_L_2 0 &gpioc 11 0>,
|
||||||
|
<ST_MORPHO_L_3 0 &gpioc 12 0>,
|
||||||
|
<ST_MORPHO_L_4 0 &gpiod 2 0>,
|
||||||
|
<ST_MORPHO_L_13 0 &gpioa 13 0>, /* SB40=ON, SB41=ON */
|
||||||
|
<ST_MORPHO_L_15 0 &gpioa 14 0>, /* SB40=ON, SB41=ON */
|
||||||
|
<ST_MORPHO_L_17 0 &gpioa 15 0>,
|
||||||
|
<ST_MORPHO_L_23 0 &gpioc 13 0>,
|
||||||
|
<ST_MORPHO_L_25 0 &gpioc 14 0>,
|
||||||
|
<ST_MORPHO_L_27 0 &gpioc 15 0>,
|
||||||
|
<ST_MORPHO_L_28 0 &gpioa 0 0>,
|
||||||
|
<ST_MORPHO_L_29 0 &gpiof 0 0>,
|
||||||
|
<ST_MORPHO_L_30 0 &gpioa 1 0>,
|
||||||
|
<ST_MORPHO_L_31 0 &gpiof 1 0>,
|
||||||
|
<ST_MORPHO_L_32 0 &gpiob 1 0>,
|
||||||
|
<ST_MORPHO_L_34 0 &gpiob 0 0>,
|
||||||
|
<ST_MORPHO_L_35 0 &gpioc 2 0>,
|
||||||
|
<ST_MORPHO_L_36 0 &gpioc 1 0>,
|
||||||
|
<ST_MORPHO_L_37 0 &gpioc 3 0>,
|
||||||
|
<ST_MORPHO_L_38 0 &gpioc 0 0>,
|
||||||
|
|
||||||
|
<ST_MORPHO_R_2 0 &gpioa 9 0>,
|
||||||
|
<ST_MORPHO_R_3 0 &gpiob 6 0>,
|
||||||
|
<ST_MORPHO_R_4 0 &gpioa 12 0>,
|
||||||
|
<ST_MORPHO_R_5 0 &gpiob 7 0>,
|
||||||
|
<ST_MORPHO_R_6 0 &gpioc 5 0>,
|
||||||
|
<ST_MORPHO_R_11 0 &gpioa 5 0>,
|
||||||
|
<ST_MORPHO_R_12 0 &gpioa 12 0>, /* SB13=ON, SB17=ON */
|
||||||
|
<ST_MORPHO_R_13 0 &gpioa 6 0>,
|
||||||
|
<ST_MORPHO_R_14 0 &gpioa 11 0>, /* SB13=ON, SB17=ON */
|
||||||
|
<ST_MORPHO_R_15 0 &gpioa 7 0>,
|
||||||
|
<ST_MORPHO_R_16 0 &gpiob 12 0>,
|
||||||
|
<ST_MORPHO_R_17 0 &gpioc 9 0>,
|
||||||
|
<ST_MORPHO_R_19 0 &gpioc 6 0>,
|
||||||
|
<ST_MORPHO_R_21 0 &gpioc 7 0>,
|
||||||
|
<ST_MORPHO_R_22 0 &gpiob 2 0>,
|
||||||
|
<ST_MORPHO_R_23 0 &gpioa 8 0>,
|
||||||
|
<ST_MORPHO_R_25 0 &gpiob 10 0>,
|
||||||
|
<ST_MORPHO_R_26 0 &gpiob 15 0>,
|
||||||
|
<ST_MORPHO_R_27 0 &gpiob 4 0>,
|
||||||
|
<ST_MORPHO_R_28 0 &gpiob 14 0>,
|
||||||
|
<ST_MORPHO_R_29 0 &gpiob 5 0>,
|
||||||
|
<ST_MORPHO_R_30 0 &gpiob 13 0>,
|
||||||
|
<ST_MORPHO_R_31 0 &gpiob 3 0>,
|
||||||
|
<ST_MORPHO_R_33 0 &gpioc 8 0>,
|
||||||
|
<ST_MORPHO_R_34 0 &gpioc 4 0>,
|
||||||
|
<ST_MORPHO_R_35 0 &gpiob 14 0>,
|
||||||
|
<ST_MORPHO_R_36 0 &gpiob 8 0>,
|
||||||
|
<ST_MORPHO_R_37 0 &gpiob 15 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
Loading…
Add table
Add a link
Reference in a new issue