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boards: mimxrt595: add CONFIG_MIPI_DPHY_CLK_SRC

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Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
This commit is contained in:
Derek Snell 2023-09-13 16:27:55 -04:00 • committed by Carles Cufí
commit 44885cbca5
2 changed files with 22 additions and 1 deletions
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12
soc/arm/nxp_imx/rt5xx/Kconfig.soc
View file

@ -141,4 +141,16 @@ config FLEXCOMM0_CLK_SRC_FRO
endchoice endchoice
choice MIPI_DPHY_CLK_SRC
prompt "Clock source for MIPI DPHY"
default MIPI_DPHY_CLK_SRC_AUX1_PLL
config MIPI_DPHY_CLK_SRC_AUX1_PLL
bool "AUX1_PLL is source of MIPI_DPHY clock"
config MIPI_DPHY_CLK_SRC_FRO
bool "FRO 192/96M is source of MIPI_DPHY clock"
endchoice
endif # SOC_SERIES_IMX_RT5XX endif # SOC_SERIES_IMX_RT5XX

11
soc/arm/nxp_imx/rt5xx/soc.c
View file

@ -462,12 +462,21 @@ void __weak imxrt_pre_init_display_interface(void)
* We set the divider of the PFD3 output of the SYSPLL, which has a * We set the divider of the PFD3 output of the SYSPLL, which has a
* fixed multiplied of 18, and use this output frequency for the DPHY. * fixed multiplied of 18, and use this output frequency for the DPHY.
*/ */
#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL
/* Note: AUX1 PLL clock is system pll clock * 18 / pfd.
* system pll clock is configured at 528MHz by default.
*/
CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK); CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK);
CLOCK_InitSysPfd(kCLOCK_Pfd3, CLOCK_InitSysPfd(kCLOCK_Pfd3,
((CLOCK_GetSysPllFreq() * 18ull) / ((CLOCK_GetSysPllFreq() * 18ull) /
((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))))); ((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)))));
CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1); CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO)
CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK);
CLOCK_SetClkDiv(kCLOCK_DivDphyClk,
(CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)));
#endif
/* Clear DSI control reset (Note that DPHY reset is cleared later)*/ /* Clear DSI control reset (Note that DPHY reset is cleared later)*/
RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
} }