diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.soc b/soc/arm/nxp_imx/rt5xx/Kconfig.soc
index c2e8fecffae..35b86c2e903 100644
--- a/soc/arm/nxp_imx/rt5xx/Kconfig.soc
+++ b/soc/arm/nxp_imx/rt5xx/Kconfig.soc
@@ -141,4 +141,16 @@ config FLEXCOMM0_CLK_SRC_FRO
 
 endchoice
 
+choice MIPI_DPHY_CLK_SRC
+	prompt "Clock source for MIPI DPHY"
+	default MIPI_DPHY_CLK_SRC_AUX1_PLL
+
+config MIPI_DPHY_CLK_SRC_AUX1_PLL
+	bool "AUX1_PLL is source of MIPI_DPHY clock"
+
+config MIPI_DPHY_CLK_SRC_FRO
+	bool "FRO 192/96M is source of MIPI_DPHY clock"
+
+endchoice
+
 endif # SOC_SERIES_IMX_RT5XX
diff --git a/soc/arm/nxp_imx/rt5xx/soc.c b/soc/arm/nxp_imx/rt5xx/soc.c
index 8df0f2fe23e..85e4a900413 100644
--- a/soc/arm/nxp_imx/rt5xx/soc.c
+++ b/soc/arm/nxp_imx/rt5xx/soc.c
@@ -462,12 +462,21 @@ void __weak imxrt_pre_init_display_interface(void)
 	 * We set the divider of the PFD3 output of the SYSPLL, which has a
 	 * fixed multiplied of 18, and use this output frequency for the DPHY.
 	 */
+
+#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL
+	/* Note: AUX1 PLL clock is system pll clock * 18 / pfd.
+	 * system pll clock is configured at 528MHz by default.
+	 */
 	CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK);
 	CLOCK_InitSysPfd(kCLOCK_Pfd3,
 		((CLOCK_GetSysPllFreq() * 18ull) /
 		((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)))));
 	CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
-
+#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO)
+	CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK);
+	CLOCK_SetClkDiv(kCLOCK_DivDphyClk,
+		(CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)));
+#endif
 	/* Clear DSI control reset (Note that DPHY reset is cleared later)*/
 	RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
 }