intel_adsp: move cavs to be a series

Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

boards/xtensa/intel_adsp_cavs15/Kconfig.board

@@ -5,4 +5,4 @@
 
 config  BOARD_INTEL_ADSP_CAVS15
 	bool "Intel ADSP CAVS 1.5"
-	depends on SOC_SERIES_INTEL_CAVS_V15
+	depends on SOC_SERIES_INTEL_ADSP_CAVS

boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig

@@ -2,7 +2,8 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V15=y
+CONFIG_SOC_INTEL_CAVS_V15=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 CONFIG_BOARD_INTEL_ADSP_CAVS15=y
 
 CONFIG_GEN_ISR_TABLES=y

boards/xtensa/intel_adsp_cavs18/Kconfig.board

@@ -5,4 +5,4 @@
 
 config  BOARD_INTEL_ADSP_CAVS18
 	bool "Intel ADSP CAVS 1.8"
-	depends on SOC_SERIES_INTEL_CAVS_V18
+	depends on SOC_SERIES_INTEL_ADSP_CAVS

boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig

@@ -2,8 +2,9 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V18=y
+CONFIG_SOC_INTEL_CAVS_V18=y
 CONFIG_BOARD_INTEL_ADSP_CAVS18=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

boards/xtensa/intel_adsp_cavs20/Kconfig.board

@@ -5,8 +5,8 @@
 
 config  BOARD_INTEL_ADSP_CAVS20
 	bool "Intel ADSP CAVS 2.0 for Ice Lake"
-	depends on SOC_SERIES_INTEL_CAVS_V20
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
 
 config  BOARD_INTEL_ADSP_CAVS20_JSL
 	bool "Intel ADSP CAVS 2.0 for Jasper Lake"
-	depends on SOC_SERIES_INTEL_CAVS_V20
+	depends on SOC_SERIES_INTEL_ADSP_CAVS

boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig

@@ -2,8 +2,9 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_SOC_INTEL_CAVS_V20=y
 CONFIG_BOARD_INTEL_ADSP_CAVS20=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig

@@ -2,8 +2,10 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_SOC_INTEL_CAVS_V20=y
 CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

boards/xtensa/intel_adsp_cavs25/Kconfig.board

@@ -5,8 +5,8 @@
 
 config  BOARD_INTEL_ADSP_CAVS25
 	bool "Intel ADSP CAVS 2.5"
-	depends on SOC_SERIES_INTEL_CAVS_V25
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
 
 config  BOARD_INTEL_ADSP_CAVS25_TGPH
 	bool "Intel ADSP CAVS 2.5 for Tiger Lake H PCH"
-	depends on SOC_SERIES_INTEL_CAVS_V25
+	depends on SOC_SERIES_INTEL_ADSP_CAVS

boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig

@@ -2,7 +2,8 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V25=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+CONFIG_SOC_INTEL_CAVS_V25=y
 CONFIG_BOARD_INTEL_ADSP_CAVS25=y
 
 CONFIG_GEN_ISR_TABLES=y

boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig

@@ -2,8 +2,10 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V25=y
+CONFIG_SOC_INTEL_CAVS_V25=y
 CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

drivers/dai/intel/ssp/ssp.c

@@ -675,7 +675,7 @@ static int dai_ssp_poll_for_register_delay(uint32_t reg, uint32_t mask,
 
 static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index)
 {
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 	uint32_t shim_reg;
 
 	shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) |
@@ -691,7 +691,7 @@ static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *d
 
 static inline void dai_ssp_pm_runtime_en_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index)
 {
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 	uint32_t shim_reg;
 
 	shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) &

drivers/dai/intel/ssp/ssp.h

@@ -40,7 +40,7 @@
 #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY	12
 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES		8
 
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 /** \brief Number of 'base' SSP ports available */
 #define DAI_INTEL_SSP_NUM_BASE			4
 /** \brief Number of 'extended' SSP ports available */

drivers/interrupt_controller/intc_cavs.c

@@ -11,13 +11,13 @@
 #include "intc_cavs.h"
 
 #if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
-#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if defined(CONFIG_SOC_INTEL_CAVS_V15)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V18)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V20)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V20)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V25)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V25)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
 #else
 #error "Must define PER_CPU_OFFSET(x) for SoC"

drivers/ipm/Kconfig

@@ -171,7 +171,7 @@ config IPM_CAVS_HOST_OUTBOX_OFFSET
 config IPM_CAVS_HOST_REGWORD
 	bool "Store first 4 bytes in IPC register"
 	depends on CAVS_IPC
-	depends on !SOC_SERIES_INTEL_CAVS_V15
+	depends on !SOC_INTEL_CAVS_V15
 	help
 	  Protocol variant.  When true, the first four bytes of a
 	  message are passed in the cAVS IDR/TDR register pair instead

drivers/mm/mm_drv_intel_adsp_tlb.c

@@ -45,7 +45,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
  * Number of significant bits in the page index (defines the size of
  * the table)
  */
-#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if defined(CONFIG_SOC_INTEL_CAVS_V15)
 # define TLB_PADDR_SIZE 9
 #else
 # define TLB_PADDR_SIZE 11

soc/xtensa/intel_adsp/Kconfig

@@ -14,6 +14,9 @@ config SOC_FAMILY
 	string
 	default "intel_adsp"
 
+# Select SoC Part No. and configuration options
+source "soc/xtensa/intel_adsp/*/Kconfig.soc"
+
 config CAVS_IPC
 	bool
 	default y if !SOF
@@ -27,11 +30,6 @@ config CAVS_CLOCK
 	  Driver for the CAVS clocks. Allow type of clock (and
 	  thus frequency) to be chosen.
 
-config INTEL_ADSP_CAVS
-	bool
-	help
-	  Indicates a CAVS SoC
-
 config HP_SRAM_RESERVE
 	int "Bytes to reserve at start of HP-SRAM"
 	default 65536
@@ -65,7 +63,6 @@ config ADSP_TRACE_SIMCALL
 	  of an enclosing simulator process.  All window contents will
 	  remain identical.
 
-# Select SoC Part No. and configuration options
+
-source "soc/xtensa/intel_adsp/*/Kconfig.soc"
 
 endif # SOC_FAMILY_INTEL_ADSP

soc/xtensa/intel_adsp/Kconfig.defconfig

@@ -20,7 +20,7 @@ config DMA_INTEL_ADSP_GPDMA
 	depends on DMA
 
 config XTENSA_CCOUNT_HZ
-	default 400000000 if SOC_SERIES_INTEL_CAVS_V25
+	default 400000000 if SOC_INTEL_CAVS_V25
 	default 200000000
 
 endif # INTEL_ADSP_CAVS

soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15

@@ -1,19 +1,18 @@
 # Copyright (c) 2020 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V15
+if SOC_INTEL_CAVS_V15
-
-config SOC_SERIES
-	string
-	default "cavs_v15"
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_apl_adsp"
 
 config SOC
-	string
+	default "intel_apl_adsp"
-	default "intel_apl_adsp" if SOC_INTEL_CAVS_V15
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V15
+	def_bool y
 
 config HP_SRAM_RESERVE
 	default 32768
@@ -65,4 +64,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif # SOC_SERIES_INTEL_CAVS_V15
+endif

soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v18

@@ -1,11 +1,8 @@
 # Copyright (c) 2020 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V18
+if SOC_INTEL_CAVS_V18
 
-config SOC_SERIES
-	string
-	default "cavs_v18"
 
 config SOC_TOOLCHAIN_NAME
 	string
@@ -13,7 +10,11 @@ config SOC_TOOLCHAIN_NAME
 
 config SOC
 	string
-	default "intel_cavs_18"
+	default "intel_cnl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V18
+	def_bool y
 
 config SMP
 	default y
@@ -57,4 +58,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif
+endif # SOC_INTEL_CAVS_V18

soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v20

@@ -1,11 +1,7 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V20
+if SOC_INTEL_CAVS_V20
-
-config SOC_SERIES
-	string
-	default "cavs_v20"
 
 config SOC_TOOLCHAIN_NAME
 	string
@@ -13,7 +9,11 @@ config SOC_TOOLCHAIN_NAME
 
 config SOC
 	string
-	default "intel_cavs_20"
+	default "intel_icl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V20
+	def_bool y
 
 config SMP
 	default y
@@ -57,4 +57,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif # SOC_SERIES_INTEL_CAVS_V20
+endif # SOC_INTEL_CAVS_V20

soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25

@@ -1,19 +1,18 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V25
+if SOC_INTEL_CAVS_V25
-
-config SOC_SERIES
-	string
-	default "cavs_v25"
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_s1000"
 
 config SOC
-	string
+	default "intel_tgl_adsp"
-	default "intel_cavs_25"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V25
+	def_bool y
 
 # Hardware has four cores, limited to two pending test fixes
 config MP_NUM_CPUS
@@ -88,4 +87,4 @@ config KERNEL_VM_SIZE
 
 endif
 
-endif # SOC_SERIES_INTEL_CAVS_V25
+endif # SOC_INTEL_CAVS_V25

soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series

@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_INTEL_ADSP_CAVS
+
+config SOC_SERIES
+	string
+	default "cavs"
+
+config INTEL_ADSP_CAVS
+	def_bool y
+
+source "soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*"
+
+endif # SOC_SERIES_INTEL_ADSP_CAVS

soc/xtensa/intel_adsp/cavs/Kconfig.series

@@ -1,15 +1,14 @@
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2017,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_INTEL_CAVS_V15
+config SOC_SERIES_INTEL_ADSP_CAVS
-	bool "Intel CAVS v1.5"
+	bool "Intel CAVS"
 	select SOC_FAMILY_INTEL_ADSP
 	select XTENSA
-	select INTEL_ADSP_CAVS
 	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select XTENSA_RESET_VECTOR
 	select XTENSA_USE_CORE_CRT1
 	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select ARCH_HAS_COHERENCE
 	help
-	  Intel CAVS v1.5
+	  Intel ADSP CAVS

soc/xtensa/intel_adsp/cavs/Kconfig.soc

@@ -0,0 +1,24 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Intel CAVS SoC Selection"
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
+
+config SOC_INTEL_CAVS_V15
+	bool "Intel Apollo Lake"
+
+config SOC_INTEL_CAVS_V18
+	bool "Intel Cannon Lake"
+	select XTENSA_WAITI_BUG
+
+config SOC_INTEL_CAVS_V20
+	bool "Intel Ice Lake"
+	select XTENSA_WAITI_BUG
+
+config SOC_INTEL_CAVS_V25
+	bool "Intel Tiger Lake"
+	select XTENSA_WAITI_BUG
+	select SCHED_IPI_SUPPORTED
+
+endchoice

soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel CAVS SoC Selection"
-
-	config SOC_INTEL_CAVS_V15
-		bool "Apollo Lake"
-		depends on SOC_SERIES_INTEL_CAVS_V15
-
-endchoice

soc/xtensa/intel_adsp/cavs_v18/Kconfig.series

@@ -1,16 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_INTEL_CAVS_V18
-	bool "Intel CAVS v1.8"
-	select SOC_FAMILY_INTEL_ADSP
-	select XTENSA
-	select INTEL_ADSP_CAVS
-	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select XTENSA_RESET_VECTOR
-	select XTENSA_USE_CORE_CRT1
-	select XTENSA_WAITI_BUG
-	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select ARCH_HAS_COHERENCE
-	help
-	  Intel CAVS v1.8

soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel CAVS SoC Selection"
-
-	config SOC_INTEL_CAVS_V18
-		bool "CAVS v1.8 SoC"
-		depends on SOC_SERIES_INTEL_CAVS_V18
-
-endchoice

soc/xtensa/intel_adsp/cavs_v18/linker.ld

@@ -1,4 +0,0 @@
-/* Copyright (c) 2021 Intel Corporation
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <cavs-link.ld>

soc/xtensa/intel_adsp/cavs_v20/Kconfig.series

@@ -1,16 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_INTEL_CAVS_V20
-	bool "Intel CAVS v2.0"
-	select SOC_FAMILY_INTEL_ADSP
-	select XTENSA
-	select INTEL_ADSP_CAVS
-	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select XTENSA_RESET_VECTOR
-	select XTENSA_USE_CORE_CRT1
-	select XTENSA_WAITI_BUG
-	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select ARCH_HAS_COHERENCE
-	help
-	  Intel CAVS v2.0

soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel CAVS SoC Selection"
-
-	config SOC_INTEL_CAVS_V20
-		bool "CAVS v2.0 SoC"
-		depends on SOC_SERIES_INTEL_CAVS_V20
-
-endchoice

soc/xtensa/intel_adsp/cavs_v20/linker.ld

@@ -1,4 +0,0 @@
-/* Copyright (c) 2021 Intel Corporation
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <cavs-link.ld>

soc/xtensa/intel_adsp/cavs_v25/Kconfig.series

@@ -1,17 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_INTEL_CAVS_V25
-	bool "Intel CAVS v2.5"
-	select SOC_FAMILY_INTEL_ADSP
-	select XTENSA
-	select INTEL_ADSP_CAVS
-	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select XTENSA_RESET_VECTOR
-	select XTENSA_USE_CORE_CRT1
-	select XTENSA_WAITI_BUG
-	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select ARCH_HAS_COHERENCE
-	select SCHED_IPI_SUPPORTED
-	help
-	  Intel CAVS v2.5

soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel CAVS SoC Selection"
-
-	config SOC_INTEL_CAVS_V25
-		bool "CAVS v2.5 SoC"
-		depends on SOC_SERIES_INTEL_CAVS_V25
-
-endchoice

soc/xtensa/intel_adsp/cavs_v25/linker.ld

@@ -1,4 +0,0 @@
-/* Copyright (c) 2021 Intel Corporation
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <cavs-link.ld>

soc/xtensa/intel_adsp/common/boot.c

@@ -41,7 +41,7 @@
 #define HOST_PAGE_SIZE		4096
 #define MANIFEST_SEGMENT_COUNT	3
 
-#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if defined(CONFIG_SOC_INTEL_CAVS_V15)
 #define PLATFORM_DISABLE_L2CACHE_AT_BOOT
 #endif
 

soc/xtensa/intel_adsp/common/clk.c

@@ -12,11 +12,11 @@ static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS];
 static struct k_spinlock lock;
 
 int cavs_clock_freq_enc[] = CAVS_CLOCK_FREQ_ENC;
-#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#ifndef CONFIG_SOC_INTEL_CAVS_V15
 int cavs_clock_freq_mask[] = CAVS_CLOCK_FREQ_MASK;
 #endif
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#ifdef CONFIG_SOC_INTEL_CAVS_V15
 static void select_cpu_clock_hw(uint32_t freq)
 {
 	uint8_t cpu_id = _current_cpu->id;
@@ -78,7 +78,7 @@ void cavs_clock_init(void)
 	uint32_t platform_lowest_freq_idx = CAVS_CLOCK_FREQ_LOWEST;
 	int i;
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 	CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO;
 	if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO)
 		CAVS_SHIM.clkctl = CAVS_SHIM.clkctl & ~CAVS_CLKCTL_WOVCRO;

soc/xtensa/intel_adsp/common/include/cavs-clk.h

@@ -49,7 +49,7 @@ struct cavs_clock_info *cavs_clocks_get(void);
 
 #define CAVS_CLOCK_FREQ_LPRO  CAVS_CLOCK_FREQ(lpro)
 #define CAVS_CLOCK_FREQ_HPRO  CAVS_CLOCK_FREQ(hpro)
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 #define CAVS_CLOCK_FREQ_WOVCRO  CAVS_CLOCK_FREQ(wovcro)
 #endif
 

soc/xtensa/intel_adsp/common/include/cavs-ipc-regs.h

@@ -60,7 +60,7 @@
  * interrupt would remain active.
  */
 struct cavs_ipc {
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#ifdef CONFIG_SOC_INTEL_CAVS_V15
 	uint32_t tdr;
 	uint32_t tdd;
 	uint32_t idr;

soc/xtensa/intel_adsp/common/include/cpu_init.h

@@ -16,7 +16,7 @@ static ALWAYS_INLINE void cpu_early_init(void)
 {
 	uint32_t reg;
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 	/* First, on cAVS 2.5 we need to power the cache SRAM banks
 	 * on!  Write a bit for each cache way in the bottom half of
 	 * the L1CCFG register and poll the top half for them to turn

soc/xtensa/intel_adsp/common/ipc.c

@@ -51,13 +51,13 @@ void z_cavs_ipc_isr(const void *devarg)
 		}
 
 		regs->tdr = CAVS_IPC_BUSY;
-		if (done && !IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+		if (done && !IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 			regs->tda = CAVS_IPC_DONE;
 		}
 	}
 
 	/* Same signal, but on different bits in 1.5 */
-	bool done = IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15) ?
+	bool done = IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15) ?
 		(regs->idd & CAVS_IPC_IDD15_DONE) : (regs->ida & CAVS_IPC_DONE);
 
 	if (done) {
@@ -65,7 +65,7 @@ void z_cavs_ipc_isr(const void *devarg)
 			devdata->done_notify(dev, devdata->done_arg);
 		}
 		k_sem_give(&devdata->sem);
-		if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+		if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 			regs->idd = CAVS_IPC_IDD15_DONE;
 		} else {
 			regs->ida = CAVS_IPC_DONE;
@@ -86,7 +86,7 @@ int cavs_ipc_init(const struct device *dev)
 	 * the other side!), then enable.
 	 */
 	config->regs->tdr = CAVS_IPC_BUSY;
-	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+	if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 		config->regs->idd = CAVS_IPC_IDD15_DONE;
 	} else {
 		config->regs->ida = CAVS_IPC_DONE;

soc/xtensa/intel_adsp/common/multiprocessing.c

@@ -108,7 +108,7 @@ __imr void z_mp_entry(void)
 	 * isn't using yet.  Manual inspection of generated code says
 	 * we're safe, but really we need a better solution here.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
 		z_xtensa_cache_flush_inv_all();
 	}
 

soc/xtensa/intel_adsp/common/multiprocessing_cavs.c

@@ -40,7 +40,7 @@ __imr void soc_mp_startup(uint32_t cpu)
 	 * disable this; otherwise our own code in soc_idc_init()
 	 * already has it unmasked.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
 		CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_IDC;
 	}
 }
@@ -49,7 +49,7 @@ void soc_start_core(int cpu_num)
 {
 	uint32_t curr_cpu = arch_proc_id();
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 	/* On cAVS v2.5, MP startup works differently.  The core has
 	 * no ROM, and starts running immediately upon receipt of an
 	 * IDC interrupt at the start of LPSRAM at 0xbe800000.  Note
@@ -89,7 +89,7 @@ void soc_start_core(int cpu_num)
 	 * turn itself off when it gets to the WAITI instruction in
 	 * the idle thread.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 		CAVS_SHIM.clkctl |= CAVS_CLKCTL_TCPLCG(cpu_num);
 	}
 	CAVS_SHIM.pwrctl |= CAVS_PWRCTL_TCPDSPPG(cpu_num);
@@ -98,7 +98,7 @@ void soc_start_core(int cpu_num)
 	 * complete initialization and be waiting for the IDC we're
 	 * about to send.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
 		k_busy_wait(CAVS15_ROM_IDC_DELAY);
 	}
 
@@ -208,7 +208,7 @@ int soc_adsp_halt_cpu(int id)
 	 * because power is controlled by the host, so synchronization
 	 * needs to be part of the application layer.
 	 */
-	while (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25) &&
+	while (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25) &&
 	       (CAVS_SHIM.pwrsts & CAVS_PWRSTS_PDSPPGS(id))) {
 	}
 	return 0;

soc/xtensa/intel_adsp/common/soc.c

@@ -23,7 +23,7 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(soc);
 
-#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#ifndef CONFIG_SOC_INTEL_CAVS_V15
 # define SHIM_GPDMA_BASE_OFFSET   0x6500
 # define SHIM_GPDMA_BASE(x)       (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
 # define SHIM_GPDMA_CLKCTL(x)     (SHIM_GPDMA_BASE(x) + 0x4)
@@ -42,7 +42,7 @@ extern void soc_mp_init(void);
 
 static __imr void power_init(void)
 {
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#ifdef CONFIG_SOC_INTEL_CAVS_V15
 	/* HP domain clocked by PLL
 	 * LP domain clocked by PLL
 	 * DSP Core 0 PLL Clock Select divide by 1

soc/xtensa/intel_adsp/common/sram.c

@@ -22,7 +22,7 @@
 #define SRAM_BANK_SIZE		(64 * 1024)
 #endif
 #define EBB_SEGMENT_SIZE	32
-#if !defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if !defined(CONFIG_SOC_INTEL_CAVS_V15)
 #define PLATFORM_INIT_HPSRAM
 #endif
 

tests/boards/intel_adsp/smoke/src/cpus.c

@@ -154,7 +154,7 @@ void halt_and_restart(int cpu)
 	/* On older hardware we need to get the host to turn the core
 	 * off.  Construct an ADSPCS with only this core disabled
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
 		cavs_ipc_send_message(CAVS_HOST_DEV, IPCCMD_ADSPCS,
 				     (all_cpus & ~BIT(cpu)) << 16);
 	}
@@ -166,7 +166,7 @@ void halt_and_restart(int cpu)
 	k_msleep(100);
 	zassert_false(alive_flag, "cpu didn't halt");
 
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
 		/* Likewise need to ask the host to turn it back on,
 		 * and give it some time to spin up before we hit it.
 		 * We don't have a return message wired to be notified
@@ -204,7 +204,7 @@ void test_cpu_halt(void)
 	arch_irq_unlock(key);
 	k_sleep(K_TICKS(0));
 
-	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+	if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 		ztest_test_skip();
 	}
 

tests/boards/intel_adsp/smoke/src/hostipc.c

@@ -71,7 +71,7 @@ void test_host_ipc(void)
 	AWAIT(msg_flag);
 
 	/* Same, but we'll complete it asynchronously (1.8+ only) */
-	if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) {
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
 		printk("Return message request, async...\n");
 		done_flag = false;
 		msg_flag = false;

tests/drivers/clock_control/cavs_clock/src/main.c

@@ -28,7 +28,7 @@ static void test_cavs_clock_driver(void)
 	cavs_clock_set_freq(CAVS_CLOCK_FREQ_HPRO);
 	check_clocks(clocks, CAVS_CLOCK_FREQ_HPRO);
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 	cavs_clock_set_freq(CAVS_CLOCK_FREQ_WOVCRO);
 	check_clocks(clocks, CAVS_CLOCK_FREQ_WOVCRO);
 #endif
@@ -49,7 +49,7 @@ static void test_cavs_clock_control(void)
 					   CAVS_CLOCK_FREQ_HPRO);
 	check_clocks(clocks, CAVS_CLOCK_FREQ_HPRO);
 
-#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#ifdef CONFIG_SOC_INTEL_CAVS_V25
 	clock_control_set_rate(dev, NULL, (clock_control_subsys_rate_t)
 					   CAVS_CLOCK_FREQ_WOVCRO);
 	check_clocks(clocks, CAVS_CLOCK_FREQ_WOVCRO);