From 43371d0414e426fdcbd27caf63fdd350685014b7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 21 Jul 2022 06:46:36 -0400 Subject: [PATCH] intel_adsp: move cavs to be a series Intel ADSP CAVS is now a proper series with all CAVS SoCs running under it. This will give us to Intel ADSP series: - CAVS - ACE v1.x Signed-off-by: Anas Nashif --- boards/xtensa/intel_adsp_cavs15/Kconfig.board | 2 +- .../intel_adsp_cavs15_defconfig | 3 ++- boards/xtensa/intel_adsp_cavs18/Kconfig.board | 2 +- .../intel_adsp_cavs18_defconfig | 3 ++- boards/xtensa/intel_adsp_cavs20/Kconfig.board | 4 ++-- .../intel_adsp_cavs20_defconfig | 3 ++- .../intel_adsp_cavs20_jsl_defconfig | 4 +++- boards/xtensa/intel_adsp_cavs25/Kconfig.board | 4 ++-- .../intel_adsp_cavs25_defconfig | 3 ++- .../intel_adsp_cavs25_tgph_defconfig | 4 +++- drivers/dai/intel/ssp/ssp.c | 4 ++-- drivers/dai/intel/ssp/ssp.h | 2 +- drivers/interrupt_controller/intc_cavs.c | 8 +++---- drivers/ipm/Kconfig | 2 +- drivers/mm/mm_drv_intel_adsp_tlb.c | 2 +- soc/xtensa/intel_adsp/Kconfig | 11 ++++----- soc/xtensa/intel_adsp/Kconfig.defconfig | 2 +- .../Kconfig.defconfig.cavs_v15} | 15 ++++++------ .../Kconfig.defconfig.cavs_v18} | 15 ++++++------ .../Kconfig.defconfig.cavs_v20} | 18 +++++++------- .../Kconfig.defconfig.cavs_v25} | 19 +++++++-------- .../intel_adsp/cavs/Kconfig.defconfig.series | 15 ++++++++++++ .../{cavs_v15 => cavs}/Kconfig.series | 9 ++++--- soc/xtensa/intel_adsp/cavs/Kconfig.soc | 24 +++++++++++++++++++ .../include/intel_apl_adsp}/adsp_memory.h | 0 .../include/intel_apl_adsp}/adsp_shim.h | 0 .../include/intel_cnl_adsp}/adsp_memory.h | 0 .../include/intel_cnl_adsp}/adsp_shim.h | 0 .../include/intel_icl_adsp}/adsp_memory.h | 0 .../include/intel_icl_adsp}/adsp_shim.h | 0 .../include/intel_tgl_adsp}/adsp_memory.h | 0 .../include/intel_tgl_adsp}/adsp_shim.h | 0 .../intel_adsp/{cavs_v15 => cavs}/linker.ld | 0 soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc | 11 --------- soc/xtensa/intel_adsp/cavs_v18/Kconfig.series | 16 ------------- soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc | 11 --------- soc/xtensa/intel_adsp/cavs_v18/linker.ld | 4 ---- soc/xtensa/intel_adsp/cavs_v20/Kconfig.series | 16 ------------- soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc | 11 --------- soc/xtensa/intel_adsp/cavs_v20/linker.ld | 4 ---- soc/xtensa/intel_adsp/cavs_v25/Kconfig.series | 17 ------------- soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc | 11 --------- soc/xtensa/intel_adsp/cavs_v25/linker.ld | 4 ---- soc/xtensa/intel_adsp/common/boot.c | 2 +- soc/xtensa/intel_adsp/common/clk.c | 6 ++--- .../intel_adsp/common/include/cavs-clk.h | 2 +- .../intel_adsp/common/include/cavs-ipc-regs.h | 2 +- .../intel_adsp/common/include/cpu_init.h | 2 +- soc/xtensa/intel_adsp/common/ipc.c | 8 +++---- .../intel_adsp/common/multiprocessing.c | 2 +- .../intel_adsp/common/multiprocessing_cavs.c | 10 ++++---- soc/xtensa/intel_adsp/common/soc.c | 4 ++-- soc/xtensa/intel_adsp/common/sram.c | 2 +- tests/boards/intel_adsp/smoke/src/cpus.c | 6 ++--- tests/boards/intel_adsp/smoke/src/hostipc.c | 2 +- .../clock_control/cavs_clock/src/main.c | 4 ++-- 56 files changed, 136 insertions(+), 199 deletions(-) rename soc/xtensa/intel_adsp/{cavs_v15/Kconfig.defconfig.series => cavs/Kconfig.defconfig.cavs_v15} (82%) rename soc/xtensa/intel_adsp/{cavs_v18/Kconfig.defconfig.series => cavs/Kconfig.defconfig.cavs_v18} (81%) rename soc/xtensa/intel_adsp/{cavs_v20/Kconfig.defconfig.series => cavs/Kconfig.defconfig.cavs_v20} (76%) rename soc/xtensa/intel_adsp/{cavs_v25/Kconfig.defconfig.series => cavs/Kconfig.defconfig.cavs_v25} (85%) create mode 100644 soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series rename soc/xtensa/intel_adsp/{cavs_v15 => cavs}/Kconfig.series (69%) create mode 100644 soc/xtensa/intel_adsp/cavs/Kconfig.soc rename soc/xtensa/intel_adsp/{cavs_v15/include => cavs/include/intel_apl_adsp}/adsp_memory.h (100%) rename soc/xtensa/intel_adsp/{cavs_v15/include => cavs/include/intel_apl_adsp}/adsp_shim.h (100%) rename soc/xtensa/intel_adsp/{cavs_v18/include => cavs/include/intel_cnl_adsp}/adsp_memory.h (100%) rename soc/xtensa/intel_adsp/{cavs_v18/include => cavs/include/intel_cnl_adsp}/adsp_shim.h (100%) rename soc/xtensa/intel_adsp/{cavs_v20/include => cavs/include/intel_icl_adsp}/adsp_memory.h (100%) rename soc/xtensa/intel_adsp/{cavs_v20/include => cavs/include/intel_icl_adsp}/adsp_shim.h (100%) rename soc/xtensa/intel_adsp/{cavs_v25/include => cavs/include/intel_tgl_adsp}/adsp_memory.h (100%) rename soc/xtensa/intel_adsp/{cavs_v25/include => cavs/include/intel_tgl_adsp}/adsp_shim.h (100%) rename soc/xtensa/intel_adsp/{cavs_v15 => cavs}/linker.ld (100%) delete mode 100644 soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/cavs_v18/Kconfig.series delete mode 100644 soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/cavs_v18/linker.ld delete mode 100644 soc/xtensa/intel_adsp/cavs_v20/Kconfig.series delete mode 100644 soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/cavs_v20/linker.ld delete mode 100644 soc/xtensa/intel_adsp/cavs_v25/Kconfig.series delete mode 100644 soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/cavs_v25/linker.ld diff --git a/boards/xtensa/intel_adsp_cavs15/Kconfig.board b/boards/xtensa/intel_adsp_cavs15/Kconfig.board index a5be1b8fbcf..01888a693b8 100644 --- a/boards/xtensa/intel_adsp_cavs15/Kconfig.board +++ b/boards/xtensa/intel_adsp_cavs15/Kconfig.board @@ -5,4 +5,4 @@ config BOARD_INTEL_ADSP_CAVS15 bool "Intel ADSP CAVS 1.5" - depends on SOC_SERIES_INTEL_CAVS_V15 + depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig b/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig index 30c3d14661f..512fc115b0c 100644 --- a/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig +++ b/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig @@ -2,7 +2,8 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V15=y +CONFIG_SOC_INTEL_CAVS_V15=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y CONFIG_BOARD_INTEL_ADSP_CAVS15=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/xtensa/intel_adsp_cavs18/Kconfig.board b/boards/xtensa/intel_adsp_cavs18/Kconfig.board index 765bfe0b095..07b6bdcea7f 100644 --- a/boards/xtensa/intel_adsp_cavs18/Kconfig.board +++ b/boards/xtensa/intel_adsp_cavs18/Kconfig.board @@ -5,4 +5,4 @@ config BOARD_INTEL_ADSP_CAVS18 bool "Intel ADSP CAVS 1.8" - depends on SOC_SERIES_INTEL_CAVS_V18 + depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig index 3eae32203da..68f2b0ea2ed 100644 --- a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig +++ b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig @@ -2,8 +2,9 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V18=y +CONFIG_SOC_INTEL_CAVS_V18=y CONFIG_BOARD_INTEL_ADSP_CAVS18=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/xtensa/intel_adsp_cavs20/Kconfig.board b/boards/xtensa/intel_adsp_cavs20/Kconfig.board index cff4b9e87b1..db1cf9e7648 100644 --- a/boards/xtensa/intel_adsp_cavs20/Kconfig.board +++ b/boards/xtensa/intel_adsp_cavs20/Kconfig.board @@ -5,8 +5,8 @@ config BOARD_INTEL_ADSP_CAVS20 bool "Intel ADSP CAVS 2.0 for Ice Lake" - depends on SOC_SERIES_INTEL_CAVS_V20 + depends on SOC_SERIES_INTEL_ADSP_CAVS config BOARD_INTEL_ADSP_CAVS20_JSL bool "Intel ADSP CAVS 2.0 for Jasper Lake" - depends on SOC_SERIES_INTEL_CAVS_V20 + depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig index cb52f92808c..ad7304e1f0b 100644 --- a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig +++ b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig @@ -2,8 +2,9 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V20=y +CONFIG_SOC_INTEL_CAVS_V20=y CONFIG_BOARD_INTEL_ADSP_CAVS20=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig index f1b0af8f468..ace4c77c3dd 100644 --- a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig +++ b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig @@ -2,8 +2,10 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V20=y +CONFIG_SOC_INTEL_CAVS_V20=y CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y + CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.board b/boards/xtensa/intel_adsp_cavs25/Kconfig.board index 947d2497d0e..275d43b3c77 100644 --- a/boards/xtensa/intel_adsp_cavs25/Kconfig.board +++ b/boards/xtensa/intel_adsp_cavs25/Kconfig.board @@ -5,8 +5,8 @@ config BOARD_INTEL_ADSP_CAVS25 bool "Intel ADSP CAVS 2.5" - depends on SOC_SERIES_INTEL_CAVS_V25 + depends on SOC_SERIES_INTEL_ADSP_CAVS config BOARD_INTEL_ADSP_CAVS25_TGPH bool "Intel ADSP CAVS 2.5 for Tiger Lake H PCH" - depends on SOC_SERIES_INTEL_CAVS_V25 + depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig index 79386de2f3a..c77824b3e1e 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig +++ b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig @@ -2,7 +2,8 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V25=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y +CONFIG_SOC_INTEL_CAVS_V25=y CONFIG_BOARD_INTEL_ADSP_CAVS25=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig index da64bfc722b..e8d7b1d5ab2 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig +++ b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig @@ -2,8 +2,10 @@ CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_CAVS_V25=y +CONFIG_SOC_INTEL_CAVS_V25=y CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH=y +CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y + CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c index a16181e1e7e..1b5250de5ce 100644 --- a/drivers/dai/intel/ssp/ssp.c +++ b/drivers/dai/intel/ssp/ssp.c @@ -675,7 +675,7 @@ static int dai_ssp_poll_for_register_delay(uint32_t reg, uint32_t mask, static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index) { -#if CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#if CONFIG_SOC_INTEL_CAVS_V15 uint32_t shim_reg; shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) | @@ -691,7 +691,7 @@ static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *d static inline void dai_ssp_pm_runtime_en_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index) { -#if CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#if CONFIG_SOC_INTEL_CAVS_V15 uint32_t shim_reg; shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) & diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h index 4b76e8467b8..7cf099659c8 100644 --- a/drivers/dai/intel/ssp/ssp.h +++ b/drivers/dai/intel/ssp/ssp.h @@ -40,7 +40,7 @@ #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY 12 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8 -#if CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#if CONFIG_SOC_INTEL_CAVS_V15 /** \brief Number of 'base' SSP ports available */ #define DAI_INTEL_SSP_NUM_BASE 4 /** \brief Number of 'extended' SSP ports available */ diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 8395dd13cc8..8aaba7b6437 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -11,13 +11,13 @@ #include "intc_cavs.h" #if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1) -#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) +#if defined(CONFIG_SOC_INTEL_CAVS_V15) #define PER_CPU_OFFSET(x) (0x40 * x) -#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18) +#elif defined(CONFIG_SOC_INTEL_CAVS_V18) #define PER_CPU_OFFSET(x) (0x40 * x) -#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V20) +#elif defined(CONFIG_SOC_INTEL_CAVS_V20) #define PER_CPU_OFFSET(x) (0x40 * x) -#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V25) +#elif defined(CONFIG_SOC_INTEL_CAVS_V25) #define PER_CPU_OFFSET(x) (0x40 * x) #else #error "Must define PER_CPU_OFFSET(x) for SoC" diff --git a/drivers/ipm/Kconfig b/drivers/ipm/Kconfig index caad71b2608..7f74585f664 100644 --- a/drivers/ipm/Kconfig +++ b/drivers/ipm/Kconfig @@ -171,7 +171,7 @@ config IPM_CAVS_HOST_OUTBOX_OFFSET config IPM_CAVS_HOST_REGWORD bool "Store first 4 bytes in IPC register" depends on CAVS_IPC - depends on !SOC_SERIES_INTEL_CAVS_V15 + depends on !SOC_INTEL_CAVS_V15 help Protocol variant. When true, the first four bytes of a message are passed in the cAVS IDR/TDR register pair instead diff --git a/drivers/mm/mm_drv_intel_adsp_tlb.c b/drivers/mm/mm_drv_intel_adsp_tlb.c index 3ec3b54228e..51adc829b57 100644 --- a/drivers/mm/mm_drv_intel_adsp_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_tlb.c @@ -45,7 +45,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0)); * Number of significant bits in the page index (defines the size of * the table) */ -#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) +#if defined(CONFIG_SOC_INTEL_CAVS_V15) # define TLB_PADDR_SIZE 9 #else # define TLB_PADDR_SIZE 11 diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig index 056f67c881c..e0c243d9a6f 100644 --- a/soc/xtensa/intel_adsp/Kconfig +++ b/soc/xtensa/intel_adsp/Kconfig @@ -14,6 +14,9 @@ config SOC_FAMILY string default "intel_adsp" +# Select SoC Part No. and configuration options +source "soc/xtensa/intel_adsp/*/Kconfig.soc" + config CAVS_IPC bool default y if !SOF @@ -27,11 +30,6 @@ config CAVS_CLOCK Driver for the CAVS clocks. Allow type of clock (and thus frequency) to be chosen. -config INTEL_ADSP_CAVS - bool - help - Indicates a CAVS SoC - config HP_SRAM_RESERVE int "Bytes to reserve at start of HP-SRAM" default 65536 @@ -65,7 +63,6 @@ config ADSP_TRACE_SIMCALL of an enclosing simulator process. All window contents will remain identical. -# Select SoC Part No. and configuration options -source "soc/xtensa/intel_adsp/*/Kconfig.soc" + endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig index ce1052fe29d..302f0a58336 100644 --- a/soc/xtensa/intel_adsp/Kconfig.defconfig +++ b/soc/xtensa/intel_adsp/Kconfig.defconfig @@ -20,7 +20,7 @@ config DMA_INTEL_ADSP_GPDMA depends on DMA config XTENSA_CCOUNT_HZ - default 400000000 if SOC_SERIES_INTEL_CAVS_V25 + default 400000000 if SOC_INTEL_CAVS_V25 default 200000000 endif # INTEL_ADSP_CAVS diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 similarity index 82% rename from soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series rename to soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 index 31b5e904c33..9cf090ceeec 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 @@ -1,19 +1,18 @@ # Copyright (c) 2020 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_INTEL_CAVS_V15 - -config SOC_SERIES - string - default "cavs_v15" +if SOC_INTEL_CAVS_V15 config SOC_TOOLCHAIN_NAME string default "intel_apl_adsp" config SOC - string - default "intel_apl_adsp" if SOC_INTEL_CAVS_V15 + default "intel_apl_adsp" + +# For backward compatibility, to be removed +config SOC_SERIES_INTEL_CAVS_V15 + def_bool y config HP_SRAM_RESERVE default 32768 @@ -65,4 +64,4 @@ config LOG_BACKEND_ADSP endif # LOG -endif # SOC_SERIES_INTEL_CAVS_V15 +endif diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v18 similarity index 81% rename from soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series rename to soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v18 index 2efc2a3ad87..7ebb878e601 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v18 @@ -1,11 +1,8 @@ # Copyright (c) 2020 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_INTEL_CAVS_V18 +if SOC_INTEL_CAVS_V18 -config SOC_SERIES - string - default "cavs_v18" config SOC_TOOLCHAIN_NAME string @@ -13,10 +10,14 @@ config SOC_TOOLCHAIN_NAME config SOC string - default "intel_cavs_18" + default "intel_cnl_adsp" + +# For backward compatibility, to be removed +config SOC_SERIES_INTEL_CAVS_V18 + def_bool y config SMP - default y + default y # FIXME: these DSPs can have more cores, but Zephyr only supports up to 2 cores on them config MP_NUM_CPUS @@ -57,4 +58,4 @@ config LOG_BACKEND_ADSP endif # LOG -endif +endif # SOC_INTEL_CAVS_V18 diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v20 similarity index 76% rename from soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series rename to soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v20 index 20fc8b7b3dc..e2ad3f5e37a 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v20 @@ -1,11 +1,7 @@ -# Copyright (c) 2020 Intel Corporation +# Copyright (c) 2020,2022 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_INTEL_CAVS_V20 - -config SOC_SERIES - string - default "cavs_v20" +if SOC_INTEL_CAVS_V20 config SOC_TOOLCHAIN_NAME string @@ -13,10 +9,14 @@ config SOC_TOOLCHAIN_NAME config SOC string - default "intel_cavs_20" + default "intel_icl_adsp" + +# For backward compatibility, to be removed +config SOC_SERIES_INTEL_CAVS_V20 + def_bool y config SMP - default y + default y # FIXME: these DSPs can have more cores, but Zephyr only supports up to 2 cores on them config MP_NUM_CPUS @@ -57,4 +57,4 @@ config LOG_BACKEND_ADSP endif # LOG -endif # SOC_SERIES_INTEL_CAVS_V20 +endif # SOC_INTEL_CAVS_V20 diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 similarity index 85% rename from soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series rename to soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 index 0eab67b0fec..ad242790437 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 @@ -1,26 +1,25 @@ -# Copyright (c) 2020 Intel Corporation +# Copyright (c) 2020,2022 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_INTEL_CAVS_V25 - -config SOC_SERIES - string - default "cavs_v25" +if SOC_INTEL_CAVS_V25 config SOC_TOOLCHAIN_NAME string default "intel_s1000" config SOC - string - default "intel_cavs_25" + default "intel_tgl_adsp" + +# For backward compatibility, to be removed +config SOC_SERIES_INTEL_CAVS_V25 + def_bool y # Hardware has four cores, limited to two pending test fixes config MP_NUM_CPUS default 2 config SMP - default y + default y config XTENSA_TIMER default n @@ -88,4 +87,4 @@ config KERNEL_VM_SIZE endif -endif # SOC_SERIES_INTEL_CAVS_V25 +endif # SOC_INTEL_CAVS_V25 diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series new file mode 100644 index 00000000000..31c6dc1a76b --- /dev/null +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series @@ -0,0 +1,15 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_INTEL_ADSP_CAVS + +config SOC_SERIES + string + default "cavs" + +config INTEL_ADSP_CAVS + def_bool y + +source "soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*" + +endif # SOC_SERIES_INTEL_ADSP_CAVS diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.series similarity index 69% rename from soc/xtensa/intel_adsp/cavs_v15/Kconfig.series rename to soc/xtensa/intel_adsp/cavs/Kconfig.series index e7c036538aa..1c4ffa61842 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.series +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.series @@ -1,15 +1,14 @@ -# Copyright (c) 2017 Intel Corporation +# Copyright (c) 2017,2022 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -config SOC_SERIES_INTEL_CAVS_V15 - bool "Intel CAVS v1.5" +config SOC_SERIES_INTEL_ADSP_CAVS + bool "Intel CAVS" select SOC_FAMILY_INTEL_ADSP select XTENSA - select INTEL_ADSP_CAVS select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" select XTENSA_RESET_VECTOR select XTENSA_USE_CORE_CRT1 select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" select ARCH_HAS_COHERENCE help - Intel CAVS v1.5 + Intel ADSP CAVS diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.soc b/soc/xtensa/intel_adsp/cavs/Kconfig.soc new file mode 100644 index 00000000000..37a99b20e13 --- /dev/null +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Intel CAVS SoC Selection" + depends on SOC_SERIES_INTEL_ADSP_CAVS + +config SOC_INTEL_CAVS_V15 + bool "Intel Apollo Lake" + +config SOC_INTEL_CAVS_V18 + bool "Intel Cannon Lake" + select XTENSA_WAITI_BUG + +config SOC_INTEL_CAVS_V20 + bool "Intel Ice Lake" + select XTENSA_WAITI_BUG + +config SOC_INTEL_CAVS_V25 + bool "Intel Tiger Lake" + select XTENSA_WAITI_BUG + select SCHED_IPI_SUPPORTED + +endchoice diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h rename to soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/adsp_shim.h b/soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v15/include/adsp_shim.h rename to soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h rename to soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/adsp_shim.h b/soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v18/include/adsp_shim.h rename to soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h rename to soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/adsp_shim.h b/soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v20/include/adsp_shim.h rename to soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h rename to soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/adsp_shim.h b/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v25/include/adsp_shim.h rename to soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs/linker.ld similarity index 100% rename from soc/xtensa/intel_adsp/cavs_v15/linker.ld rename to soc/xtensa/intel_adsp/cavs/linker.ld diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc deleted file mode 100644 index faae50c153c..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - - config SOC_INTEL_CAVS_V15 - bool "Apollo Lake" - depends on SOC_SERIES_INTEL_CAVS_V15 - -endchoice diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series deleted file mode 100644 index 5da6fe176cb..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_CAVS_V18 - bool "Intel CAVS v1.8" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select INTEL_ADSP_CAVS - select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select XTENSA_WAITI_BUG - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ARCH_HAS_COHERENCE - help - Intel CAVS v1.8 diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc deleted file mode 100644 index 71a250b19ac..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - - config SOC_INTEL_CAVS_V18 - bool "CAVS v1.8 SoC" - depends on SOC_SERIES_INTEL_CAVS_V18 - -endchoice diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld deleted file mode 100644 index 3516c4b0215..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ /dev/null @@ -1,4 +0,0 @@ -/* Copyright (c) 2021 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ -#include diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series deleted file mode 100644 index 68e06860e37..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_CAVS_V20 - bool "Intel CAVS v2.0" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select INTEL_ADSP_CAVS - select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select XTENSA_WAITI_BUG - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ARCH_HAS_COHERENCE - help - Intel CAVS v2.0 diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc deleted file mode 100644 index 0b44f61bf82..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - - config SOC_INTEL_CAVS_V20 - bool "CAVS v2.0 SoC" - depends on SOC_SERIES_INTEL_CAVS_V20 - -endchoice diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld deleted file mode 100644 index 3516c4b0215..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ /dev/null @@ -1,4 +0,0 @@ -/* Copyright (c) 2021 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ -#include diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series deleted file mode 100644 index 64f349aa03d..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_CAVS_V25 - bool "Intel CAVS v2.5" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select INTEL_ADSP_CAVS - select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select XTENSA_WAITI_BUG - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ARCH_HAS_COHERENCE - select SCHED_IPI_SUPPORTED - help - Intel CAVS v2.5 diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc deleted file mode 100644 index 04d9ca87797..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - - config SOC_INTEL_CAVS_V25 - bool "CAVS v2.5 SoC" - depends on SOC_SERIES_INTEL_CAVS_V25 - -endchoice diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld deleted file mode 100644 index 3516c4b0215..00000000000 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ /dev/null @@ -1,4 +0,0 @@ -/* Copyright (c) 2021 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ -#include diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/xtensa/intel_adsp/common/boot.c index ede7871ea68..fe872f49811 100644 --- a/soc/xtensa/intel_adsp/common/boot.c +++ b/soc/xtensa/intel_adsp/common/boot.c @@ -41,7 +41,7 @@ #define HOST_PAGE_SIZE 4096 #define MANIFEST_SEGMENT_COUNT 3 -#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) +#if defined(CONFIG_SOC_INTEL_CAVS_V15) #define PLATFORM_DISABLE_L2CACHE_AT_BOOT #endif diff --git a/soc/xtensa/intel_adsp/common/clk.c b/soc/xtensa/intel_adsp/common/clk.c index fabfbba66c6..6834e989c1c 100644 --- a/soc/xtensa/intel_adsp/common/clk.c +++ b/soc/xtensa/intel_adsp/common/clk.c @@ -12,11 +12,11 @@ static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS]; static struct k_spinlock lock; int cavs_clock_freq_enc[] = CAVS_CLOCK_FREQ_ENC; -#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#ifndef CONFIG_SOC_INTEL_CAVS_V15 int cavs_clock_freq_mask[] = CAVS_CLOCK_FREQ_MASK; #endif -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#ifdef CONFIG_SOC_INTEL_CAVS_V15 static void select_cpu_clock_hw(uint32_t freq) { uint8_t cpu_id = _current_cpu->id; @@ -78,7 +78,7 @@ void cavs_clock_init(void) uint32_t platform_lowest_freq_idx = CAVS_CLOCK_FREQ_LOWEST; int i; -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO; if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO) CAVS_SHIM.clkctl = CAVS_SHIM.clkctl & ~CAVS_CLKCTL_WOVCRO; diff --git a/soc/xtensa/intel_adsp/common/include/cavs-clk.h b/soc/xtensa/intel_adsp/common/include/cavs-clk.h index 7f306392d03..e929357548d 100644 --- a/soc/xtensa/intel_adsp/common/include/cavs-clk.h +++ b/soc/xtensa/intel_adsp/common/include/cavs-clk.h @@ -49,7 +49,7 @@ struct cavs_clock_info *cavs_clocks_get(void); #define CAVS_CLOCK_FREQ_LPRO CAVS_CLOCK_FREQ(lpro) #define CAVS_CLOCK_FREQ_HPRO CAVS_CLOCK_FREQ(hpro) -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 #define CAVS_CLOCK_FREQ_WOVCRO CAVS_CLOCK_FREQ(wovcro) #endif diff --git a/soc/xtensa/intel_adsp/common/include/cavs-ipc-regs.h b/soc/xtensa/intel_adsp/common/include/cavs-ipc-regs.h index 8feefa0ac47..a7b9bd74895 100644 --- a/soc/xtensa/intel_adsp/common/include/cavs-ipc-regs.h +++ b/soc/xtensa/intel_adsp/common/include/cavs-ipc-regs.h @@ -60,7 +60,7 @@ * interrupt would remain active. */ struct cavs_ipc { -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#ifdef CONFIG_SOC_INTEL_CAVS_V15 uint32_t tdr; uint32_t tdd; uint32_t idr; diff --git a/soc/xtensa/intel_adsp/common/include/cpu_init.h b/soc/xtensa/intel_adsp/common/include/cpu_init.h index e277a2e164d..55293cf3fc0 100644 --- a/soc/xtensa/intel_adsp/common/include/cpu_init.h +++ b/soc/xtensa/intel_adsp/common/include/cpu_init.h @@ -16,7 +16,7 @@ static ALWAYS_INLINE void cpu_early_init(void) { uint32_t reg; -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 /* First, on cAVS 2.5 we need to power the cache SRAM banks * on! Write a bit for each cache way in the bottom half of * the L1CCFG register and poll the top half for them to turn diff --git a/soc/xtensa/intel_adsp/common/ipc.c b/soc/xtensa/intel_adsp/common/ipc.c index 8e8a29b356e..9e6b7cb3546 100644 --- a/soc/xtensa/intel_adsp/common/ipc.c +++ b/soc/xtensa/intel_adsp/common/ipc.c @@ -51,13 +51,13 @@ void z_cavs_ipc_isr(const void *devarg) } regs->tdr = CAVS_IPC_BUSY; - if (done && !IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (done && !IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { regs->tda = CAVS_IPC_DONE; } } /* Same signal, but on different bits in 1.5 */ - bool done = IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15) ? + bool done = IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15) ? (regs->idd & CAVS_IPC_IDD15_DONE) : (regs->ida & CAVS_IPC_DONE); if (done) { @@ -65,7 +65,7 @@ void z_cavs_ipc_isr(const void *devarg) devdata->done_notify(dev, devdata->done_arg); } k_sem_give(&devdata->sem); - if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { regs->idd = CAVS_IPC_IDD15_DONE; } else { regs->ida = CAVS_IPC_DONE; @@ -86,7 +86,7 @@ int cavs_ipc_init(const struct device *dev) * the other side!), then enable. */ config->regs->tdr = CAVS_IPC_BUSY; - if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { config->regs->idd = CAVS_IPC_IDD15_DONE; } else { config->regs->ida = CAVS_IPC_DONE; diff --git a/soc/xtensa/intel_adsp/common/multiprocessing.c b/soc/xtensa/intel_adsp/common/multiprocessing.c index c1f0d4a6c6d..2b352b76002 100644 --- a/soc/xtensa/intel_adsp/common/multiprocessing.c +++ b/soc/xtensa/intel_adsp/common/multiprocessing.c @@ -108,7 +108,7 @@ __imr void z_mp_entry(void) * isn't using yet. Manual inspection of generated code says * we're safe, but really we need a better solution here. */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) { z_xtensa_cache_flush_inv_all(); } diff --git a/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c b/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c index 359fdf5fd3d..ce12fe774eb 100644 --- a/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c +++ b/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c @@ -40,7 +40,7 @@ __imr void soc_mp_startup(uint32_t cpu) * disable this; otherwise our own code in soc_idc_init() * already has it unmasked. */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) { CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_IDC; } } @@ -49,7 +49,7 @@ void soc_start_core(int cpu_num) { uint32_t curr_cpu = arch_proc_id(); -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 /* On cAVS v2.5, MP startup works differently. The core has * no ROM, and starts running immediately upon receipt of an * IDC interrupt at the start of LPSRAM at 0xbe800000. Note @@ -89,7 +89,7 @@ void soc_start_core(int cpu_num) * turn itself off when it gets to the WAITI instruction in * the idle thread. */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { CAVS_SHIM.clkctl |= CAVS_CLKCTL_TCPLCG(cpu_num); } CAVS_SHIM.pwrctl |= CAVS_PWRCTL_TCPDSPPG(cpu_num); @@ -98,7 +98,7 @@ void soc_start_core(int cpu_num) * complete initialization and be waiting for the IDC we're * about to send. */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) { k_busy_wait(CAVS15_ROM_IDC_DELAY); } @@ -208,7 +208,7 @@ int soc_adsp_halt_cpu(int id) * because power is controlled by the host, so synchronization * needs to be part of the application layer. */ - while (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25) && + while (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25) && (CAVS_SHIM.pwrsts & CAVS_PWRSTS_PDSPPGS(id))) { } return 0; diff --git a/soc/xtensa/intel_adsp/common/soc.c b/soc/xtensa/intel_adsp/common/soc.c index 68264502472..1da5b9212b5 100644 --- a/soc/xtensa/intel_adsp/common/soc.c +++ b/soc/xtensa/intel_adsp/common/soc.c @@ -23,7 +23,7 @@ #include LOG_MODULE_REGISTER(soc); -#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#ifndef CONFIG_SOC_INTEL_CAVS_V15 # define SHIM_GPDMA_BASE_OFFSET 0x6500 # define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) # define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) @@ -42,7 +42,7 @@ extern void soc_mp_init(void); static __imr void power_init(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15 +#ifdef CONFIG_SOC_INTEL_CAVS_V15 /* HP domain clocked by PLL * LP domain clocked by PLL * DSP Core 0 PLL Clock Select divide by 1 diff --git a/soc/xtensa/intel_adsp/common/sram.c b/soc/xtensa/intel_adsp/common/sram.c index 0a9306f9d70..34dd5e48385 100644 --- a/soc/xtensa/intel_adsp/common/sram.c +++ b/soc/xtensa/intel_adsp/common/sram.c @@ -22,7 +22,7 @@ #define SRAM_BANK_SIZE (64 * 1024) #endif #define EBB_SEGMENT_SIZE 32 -#if !defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) +#if !defined(CONFIG_SOC_INTEL_CAVS_V15) #define PLATFORM_INIT_HPSRAM #endif diff --git a/tests/boards/intel_adsp/smoke/src/cpus.c b/tests/boards/intel_adsp/smoke/src/cpus.c index 61f4b23ae48..04e096f0fe4 100644 --- a/tests/boards/intel_adsp/smoke/src/cpus.c +++ b/tests/boards/intel_adsp/smoke/src/cpus.c @@ -154,7 +154,7 @@ void halt_and_restart(int cpu) /* On older hardware we need to get the host to turn the core * off. Construct an ADSPCS with only this core disabled */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) { cavs_ipc_send_message(CAVS_HOST_DEV, IPCCMD_ADSPCS, (all_cpus & ~BIT(cpu)) << 16); } @@ -166,7 +166,7 @@ void halt_and_restart(int cpu) k_msleep(100); zassert_false(alive_flag, "cpu didn't halt"); - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) { /* Likewise need to ask the host to turn it back on, * and give it some time to spin up before we hit it. * We don't have a return message wired to be notified @@ -204,7 +204,7 @@ void test_cpu_halt(void) arch_irq_unlock(key); k_sleep(K_TICKS(0)); - if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { ztest_test_skip(); } diff --git a/tests/boards/intel_adsp/smoke/src/hostipc.c b/tests/boards/intel_adsp/smoke/src/hostipc.c index ae2e9e98548..b1e9a73bb55 100644 --- a/tests/boards/intel_adsp/smoke/src/hostipc.c +++ b/tests/boards/intel_adsp/smoke/src/hostipc.c @@ -71,7 +71,7 @@ void test_host_ipc(void) AWAIT(msg_flag); /* Same, but we'll complete it asynchronously (1.8+ only) */ - if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { + if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) { printk("Return message request, async...\n"); done_flag = false; msg_flag = false; diff --git a/tests/drivers/clock_control/cavs_clock/src/main.c b/tests/drivers/clock_control/cavs_clock/src/main.c index 4b5752aa88f..83899b42ef0 100644 --- a/tests/drivers/clock_control/cavs_clock/src/main.c +++ b/tests/drivers/clock_control/cavs_clock/src/main.c @@ -28,7 +28,7 @@ static void test_cavs_clock_driver(void) cavs_clock_set_freq(CAVS_CLOCK_FREQ_HPRO); check_clocks(clocks, CAVS_CLOCK_FREQ_HPRO); -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 cavs_clock_set_freq(CAVS_CLOCK_FREQ_WOVCRO); check_clocks(clocks, CAVS_CLOCK_FREQ_WOVCRO); #endif @@ -49,7 +49,7 @@ static void test_cavs_clock_control(void) CAVS_CLOCK_FREQ_HPRO); check_clocks(clocks, CAVS_CLOCK_FREQ_HPRO); -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25 +#ifdef CONFIG_SOC_INTEL_CAVS_V25 clock_control_set_rate(dev, NULL, (clock_control_subsys_rate_t) CAVS_CLOCK_FREQ_WOVCRO); check_clocks(clocks, CAVS_CLOCK_FREQ_WOVCRO);