boards: variscite: Add Variscite VAR-SOM-MX8M-PLUS board
Add Variscite VAR-SOM-MX8M-PLUS board support. This SoM is based on NXP's i.MX8M Plus SoC. It includes Cortex-A53 and Cortex-M7 support. Signed-off-by: Andre Morishita <andre.m@variscite.com>
This commit is contained in:
Andre Morishita
Fabio Baltieri
parent
eabb0b5cfc
commit
40a3d1e365
16 changed files with 693 additions and 0 deletions
8
boards/variscite/imx8mp_var_som/Kconfig.imx8mp_var_som
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8
boards/variscite/imx8mp_var_som/Kconfig.imx8mp_var_som
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# Copyright 2025 Variscite Ltd.
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# Copyright 2021-2022, 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_IMX8MP_VAR_SOM
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select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_VAR_SOM_MIMX8ML8_A53
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select SOC_MIMX8ML8_M7 if BOARD_IMX8MP_VAR_SOM_MIMX8ML8_M7 || BOARD_IMX8MP_VAR_SOM_MIMX8ML8_M7_DDR
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select SOC_PART_NUMBER_MIMX8ML8DVNLZ
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14
boards/variscite/imx8mp_var_som/board.cmake
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boards/variscite/imx8mp_var_som/board.cmake
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#
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# Copyright 2025 Variscite Ltd.
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# Copyright (c) 2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if(CONFIG_SOC_MIMX8ML8_M7)
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board_set_debugger_ifnset(jlink)
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board_set_flasher_ifnset(jlink)
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board_runner_args(jlink "--device=MIMX8ML8_M7")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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endif()
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9
boards/variscite/imx8mp_var_som/board.yml
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boards/variscite/imx8mp_var_som/board.yml
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boards:
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- name: imx8mp_var_som
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full_name: VAR-SOM-MX8M-PLUS
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vendor: variscite
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socs:
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- name: mimx8ml8
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variants:
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- name: ddr
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cpucluster: m7
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BIN
boards/variscite/imx8mp_var_som/doc/imx8mp_var_som.webp
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BIN
boards/variscite/imx8mp_var_som/doc/imx8mp_var_som.webp
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Binary file not shown.
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After Width: | Height: | Size: 50 KiB |
277
boards/variscite/imx8mp_var_som/doc/index.rst
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boards/variscite/imx8mp_var_som/doc/index.rst
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.. zephyr:board:: imx8mp_var_som
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Overview
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********
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Variscite's VAR-SOM-MX8M-PLUS System on Module (SoM) is based on the i.MX 8M Plus family,
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which is a set of NXP products built to achieve both high performance and low power
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consumption and relies on a powerful, fully coherent core complex based on a quad Cortex®-A53
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cluster and Cortex®-M7 low-power coprocessor, audio digital signal processor, machine learning
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and graphics accelerators.
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Zephyr OS is ported to run on either the Cortex®-A53 or the Cortex®-M7.
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Specs Summary
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***************
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- CPU
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- NXP i.MX8M Plus:
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- Up to 4x Cortex®-A53 @ 1.8GHz
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- 1x Cortex®-M7 @ 800 MHz
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- 1x NPU 2.3 TOPS
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- Memory
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- Up to 8GB LPDDR4 RAM @ 2000MHz
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- 8-bit up to 128GB eMMC boot and storage
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- GPU
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- 3D: Vivante™ GC7000UltraLite (2 shaders) OpenGL ES 3.0, OpenCL1.2, Vulkan
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- 2D: Vivante™ GC520L
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- NPU (Neural Processing Unit)
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- 2.3 TOPS Neural Network performance
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- Display
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- 2x LVDS interface 4-lane each up to 1080p60
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- HDMI 2.0a up to 4Kp30
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- 1x MIPI DSI with up to 4 data lanes 1080p60
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- Network
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- 2x 10/100/1000 Mbit/s Ethernet Interface
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- Certified Wi-Fi 6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4
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- Bluetooth/BLE 5.4
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- Camera
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- Up to 2x MIPI CSI – CMOS Serial camera Interface 4 lanes
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- 375 Mpixel/s HDR ISP (Image Sensor Processor)
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- Audio
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- Headphones
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- Microphone: Digital, Analog (stereo)
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- 6x I2S(SAI), S/PDIF RX TX, PDM 8CH, Line In/Out
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- USB
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- 2x USB 3.0/2.0 Host/Device
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- Serial interfaces
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- SPI: x3
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- I2C: x5
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- UART: x4, up to 5 Mbps
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- CAN: x2
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- Temperature range
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- -40°C to 85°C
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More information about the SoM can be found at the
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`Variscite Wiki`_ and
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`Variscite website`_.
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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.. note::
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It is recommended to disable peripherals used by the M7 core on the Linux host.
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Devices
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========
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System Clock
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------------
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This board configuration uses a system clock frequency of 8 MHz.
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The M7 core is configured to run at an 800 MHz clock speed.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel with the
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CPU's UART4.
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Programming and Debugging (A53)
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*******************************
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Copy the compiled ``zephyr.bin`` to the boot directory of the SD card and
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plug the SD card into the board. Power it up and stop the U-Boot execution at
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prompt.
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Use U-Boot to load and run zephyr.bin on the Cortex-A53:
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.. code-block:: console
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load mmc $mmcdev:$mmcpart $loadaddr /boot/zephyr.bin
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dcache flush; icache flush; go $loadaddr
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Use this configuration to run basic Zephyr applications and kernel tests,
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for example, with the :zephyr:code-sample:`hello_world` sample:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:host-os: unix
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:board: imx8mp_var_som/mimx8ml8/a53
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:goals: build
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This will build an image with the hello_world sample app. When loaded and executed
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it will display the following ram console output:
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.. code-block:: console
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*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
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Hello World! imx8mp_var_som/mimx8ml8/a53
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Programming and Debugging (M7)
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******************************
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.. zephyr:board-supported-runners::
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The VAR-SOM-MX8M-PLUS don't have QSPI flash for the M7, and it needs to be
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started by the A53 core. The A53 core is responsible to load the M7 binary
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application into the RAM, put the M7 in reset, set the M7 Program Counter and
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Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at
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bootloader level or after the Linux system has booted.
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The M7 can use up to 3 different RAMs (currently, only two configurations are
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supported: ITCM and DDR). These are the memory mapping for A53 and M7:
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
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+============+=========================+========================+=======================+======================+
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| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| DDR | 0x80000000-0x803FFFFF | 0x7E200000-0x7E3FFFFF | 0x7E000000-0x7E1FFFFF | 2MB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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For more information about memory mapping see the
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`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3)
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At compilation time you have to choose which RAM will be used. This
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configuration is done based on board name (e.g. imx8mp_var_som/mimx8ml8/m7
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for ITCM and imx8mp_var_som/mimx8ml8/m7/ddr for DDR).
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There are two methods to load M7 Core images: U-Boot command and Linux remoteproc.
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Load and Run M7 Zephyr Image from U-Boot
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========================================
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Load and run Zephyr on M7 from A53 using U-Boot by copying the compiled
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``zephyr.bin`` to the boot directory of the SD card and plug the SD
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card into the board. Power it up and stop the U-Boot execution at prompt.
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Load the M7 binary onto the desired memory and start its execution using:
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ITCM
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====
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.. code-block:: console
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load mmc 1:1 0x48000000 /boot/zephyr.bin
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cp.b 0x48000000 0x7e0000 20000
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bootaux 0x7e0000
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DDR
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===
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.. code-block:: console
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load mmc 1:1 0x7b000000 /boot/zephyr.bin
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dcache flush
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bootaux 0x7b000000
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Load and Run M7 Zephyr Image by using Linux remoteproc
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======================================================
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Transfer built binaries ``zephyr.bin`` and ``zephyr.elf`` to the SoM's ``/boot`` and
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``/lib/firmware`` respectively using ``scp`` or through an USB drive.
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It is possible to execute Zephyr binaries using Variscite remoteproc scripts made
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for MCUXpresso binaries:
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.. code-block:: console
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root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-linux -f /lib/firmware/zephyr.elf
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[ 212.888118] remoteproc remoteproc0: powering up imx-rproc
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[ 212.899215] remoteproc remoteproc0: Booting fw image zephyr.elf, size 515836
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[ 212.912070] remoteproc remoteproc0: No resource table in elf
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[ 213.444675] remoteproc remoteproc0: remote processor imx-rproc is now up
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Which should yield the following result on the UART4 serial console:
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.. code-block:: console
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*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
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Hello World! imx8mp_var_som/mimx8ml8/m7
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If the device tree dedicated to be used with Cortex-M7 applications is not being
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currently used, the script will give instructions on how to do so:
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.. code-block:: console
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Error: /sys/class/remoteproc/remoteproc0 not found.
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Please enable remoteproc driver.
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Most likely you need to use the correct device tree, for example:
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fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb && reboot
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You can also configure U-Boot to load firmware on boot:
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.. code-block:: console
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root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-u-boot -f /boot/zephyr.bin
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Configuring for TCM memory
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+ fw_setenv m7_addr 0x7E0000
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+ fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb
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+ fw_setenv use_m7 yes
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+ fw_setenv m7_bin zephyr.bin
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Finished: Please reboot, the m7 firmware will run during U-Boot
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For more information about Variscite remoteproc scripts and general Cortex-M7
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support, visit `Variscite Wiki`_.
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Debugging
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=========
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VAR-SOM-MX8M-PLUS board can be debugged by connecting an external
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JLink JTAG debugger to the 14-pin header on the top left side of
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the SoM and to the PC. Then the application can be debugged using
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the usual way.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: imx8mp_var_som/mimx8ml8/m7
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:goals: debug
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Open a serial terminal, step through the application in your debugger, and you
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should see the following message in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
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Hello World! imx8mp_var_som/mimx8ml8/m7
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References
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==========
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- `Variscite Wiki`_
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- `Variscite website`_
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- `i.MX 8M Applications Processor Reference Manual`_
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.. _Variscite Wiki:
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https://variwiki.com/index.php?title=VAR-SOM-MX8M-PLUS
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.. _Variscite website:
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https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-mx8m-plus-nxp-i-mx-8m-plus
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.. _i.MX 8M Applications Processor Reference Manual:
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https://www.nxp.com/webapp/Download?colCode=IMX8MPRM
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40
boards/variscite/imx8mp_var_som/imx8mp_var_som-pinctrl.dtsi
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40
boards/variscite/imx8mp_var_som/imx8mp_var_som-pinctrl.dtsi
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/*
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* Copyright 2025 Variscite Ltd.
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* Copyright 2022-2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
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&pinctrl {
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uart1_default: uart1_default {
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group0 {
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pinmux = <&iomuxc_uart1_rxd_uart_rx_uart1_rx>,
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<&iomuxc_uart1_txd_uart_tx_uart1_tx>;
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bias-pull-up;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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};
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uart3_default: uart3_default {
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group0 {
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pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>,
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<&iomuxc_uart3_txd_uart_tx_uart3_tx>;
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bias-pull-up;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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};
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uart4_default: uart4_default {
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group0 {
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pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
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<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
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bias-pull-up;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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};
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};
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/*
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* Copyright 2025 Variscite Ltd.
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_mimx8mp_a53.dtsi>
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#include "imx8mp_var_som-pinctrl.dtsi"
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "Variscite VAR-SOM-MX8M-PLUS A53";
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compatible = "fsl,mimx8mp";
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chosen {
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zephyr,console = &uart4;
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zephyr,shell-uart = &uart4;
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/* sram node actually locates at DDR DRAM */
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zephyr,sram = &dram;
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};
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cpus {
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cpu@0 {
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status = "disabled";
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};
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cpu@1 {
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status = "disabled";
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};
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cpu@2 {
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status = "disabled";
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};
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};
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dram: memory@40480000 {
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reg = <0x40480000 DT_SIZE_M(1)>;
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};
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aliases {
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led0 = &blinky0;
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sw0 = &button0;
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};
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leds {
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compatible = "gpio-leds";
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blinky0: blinky_0 {
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gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
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};
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};
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keys {
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compatible = "gpio-keys";
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button0: btn_0 {
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label = "BTN0";
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gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>;
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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};
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&uart4 {
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status = "okay";
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current-speed = <115200>;
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clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
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pinctrl-0 = <&uart4_default>;
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pinctrl-names = "default";
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};
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&gpio3 {
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status = "okay";
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};
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@ -0,0 +1,21 @@
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#
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# Copyright 2025 Variscite Ltd.
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# Copyright 2024 NXP
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#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: imx8mp_var_som/mimx8ml8/a53
|
||||
name: Variscite VAR-SOM-MX8M-PLUS A53
|
||||
type: mcu
|
||||
arch: arm64
|
||||
toolchain:
|
||||
- zephyr
|
||||
- cross-compile
|
||||
ram: 1024
|
||||
supported:
|
||||
- uart
|
||||
- net
|
||||
testing:
|
||||
ignore_tags:
|
||||
- bluetooth
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright 2025 Variscite Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# ARM Options
|
||||
CONFIG_AARCH64_IMAGE_HEADER=y
|
||||
CONFIG_ARMV8_A_NS=y
|
||||
CONFIG_ARM64_VA_BITS_36=y
|
||||
CONFIG_ARM64_PA_BITS_36=y
|
||||
|
||||
# Cache Options
|
||||
CONFIG_CACHE_MANAGEMENT=y
|
||||
CONFIG_DCACHE_LINE_SIZE_DETECT=y
|
||||
CONFIG_ICACHE_LINE_SIZE_DETECT=y
|
||||
|
||||
# Zephyr Kernel Configuration
|
||||
CONFIG_XIP=n
|
||||
CONFIG_KERNEL_DIRECT_MAP=y
|
||||
|
||||
# Serial Drivers
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# Enable Console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright 2025 Variscite Ltd.
|
||||
* Copyright (c) 2021, Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <nxp/nxp_imx8ml_m7.dtsi>
|
||||
#include "imx8mp_var_som-pinctrl.dtsi"
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
|
||||
/ {
|
||||
model = "Variscite VAR-SOM-MX8M-PLUS M7";
|
||||
compatible = "nxp,imx8mp_var_som";
|
||||
|
||||
chosen {
|
||||
/* TCM */
|
||||
zephyr,flash = &itcm;
|
||||
zephyr,sram = &dtcm;
|
||||
|
||||
zephyr,console = &uart4;
|
||||
zephyr,shell-uart = &uart4;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led0 = &blinky0;
|
||||
sw0 = &button0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
blinky0: blinky_0 {
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button0: btn_0 {
|
||||
label = "BTN0";
|
||||
gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
pinctrl-0 = <&uart4_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#
|
||||
# Copyright 2025 Variscite Ltd.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: imx8mp_var_som/mimx8ml8/m7
|
||||
name: Variscite VAR-SOM-MX8M-PLUS M7
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 128
|
||||
flash: 128
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
supported:
|
||||
- uart
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright 2025 Variscite Ltd.
|
||||
* Copyright (c) 2021, Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <nxp/nxp_imx8ml_m7.dtsi>
|
||||
#include "imx8mp_var_som-pinctrl.dtsi"
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
|
||||
/delete-node/ &ddr_code;
|
||||
/delete-node/ &ddr_sys;
|
||||
|
||||
/ {
|
||||
model = "Variscite VAR-SOM-MX8M-PLUS M7 (DDR)";
|
||||
compatible = "nxp,imx8mp_var_som";
|
||||
|
||||
chosen {
|
||||
/* DDR */
|
||||
zephyr,flash = &ddr_code;
|
||||
zephyr,sram = &ddr_sys;
|
||||
|
||||
zephyr,console = &uart4;
|
||||
zephyr,shell-uart = &uart4;
|
||||
};
|
||||
|
||||
soc {
|
||||
ddr_code: code@7b000000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-code-bus";
|
||||
reg = <0x7b000000 DT_SIZE_M(2)>;
|
||||
};
|
||||
|
||||
ddr_sys: memory@7b200000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x7b200000 DT_SIZE_M(2)>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led0 = &blinky0;
|
||||
sw0 = &button0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
blinky0: blinky_0 {
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button0: btn_0 {
|
||||
label = "BTN0";
|
||||
gpios = <&gpio3 6 (GPIO_PULL_UP|GPIO_ACTIVE_LOW)>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
pinctrl-0 = <&uart4_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#
|
||||
# Copyright 2025 Variscite Ltd.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: imx8mp_var_som/mimx8ml8/m7/ddr
|
||||
name: Variscite VAR-SOM-MX8M-PLUS M7 (DDR)
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 2048
|
||||
flash: 2048
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
supported:
|
||||
- uart
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#
|
||||
# Copyright 2025 Variscite Ltd.
|
||||
# Copyright (c) 2021, Laird Connectivity
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_XIP=y
|
||||
CONFIG_CODE_DDR=y
|
||||
CONFIG_FLASH_BASE_ADDRESS=0x7b000000
|
||||
CONFIG_FLASH_SIZE=2048
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Copyright 2025 Variscite Ltd.
|
||||
# Copyright (c) 2021, Laird Connectivity
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_XIP=y
|
||||
CONFIG_CODE_ITCM=y
|
||||
10
boards/variscite/index.rst
Normal file
10
boards/variscite/index.rst
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
.. _boards-variscite:
|
||||
|
||||
Variscite
|
||||
#########
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:glob:
|
||||
|
||||
**/*
|
||||
Loading…
Add table
Add a link
Reference in a new issue