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tests: drivers: clock_control: Add PLL fracn test

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Added a test case that generates a 160 MHz system clock
using a 16777216 Hz HSE clock and also using a 16 MHz HSI

Signed-off-by: Jatty Andriean <jandriea@outlook.com>
This commit is contained in:
Jatty Andriean 2023-09-26 07:57:22 +00:00 • committed by Carles Cufí
commit 3eea17c5de
3 changed files with 80 additions and 0 deletions
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40
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hse_fracn_160.overlay Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2023 Jatty Andriean <jandriea@outlook.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE is not implemented on available boards, hence:
* This configuration is only available for build
*/
&clk_hse {
status = "okay";
clock-frequency = <16777216>;
};
&pll1 {
div-m = <2>;
mul-n = <19>;
div-p = <1>;
div-q = <1>;
div-r = <1>;
fracn = <602>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hsi_fracn_160.overlay Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (c) 2023 Jatty Andriean <jandriea@outlook.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll1 {
div-m = <1>;
mul-n = <20>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
fracn = <0>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

6
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
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@ -24,3 +24,9 @@ tests:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay" extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay"
# Build only as HSE not implemened on available boards # Build only as HSE not implemened on available boards
build_only: true build_only: true
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_fracn_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_fracn_160.overlay"
# Build only as HSE not implemened on available boards
build_only: true
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_fracn_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_160.overlay"