diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hse_fracn_160.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hse_fracn_160.overlay
new file mode 100644
index 00000000000..014ef48fd7d
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hse_fracn_160.overlay
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023 Jatty Andriean <jandriea@outlook.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+/*
+ * Warning: HSE is not implemented on available boards, hence:
+ *          This configuration is only available for build
+ */
+
+&clk_hse {
+	status = "okay";
+	clock-frequency = <16777216>;
+};
+
+&pll1 {
+	div-m = <2>;
+	mul-n = <19>;
+	div-p = <1>;
+	div-q = <1>;
+	div-r = <1>;
+	fracn = <602>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(160)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb3-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hsi_fracn_160.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hsi_fracn_160.overlay
new file mode 100644
index 00000000000..ffc339ad184
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hsi_fracn_160.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023 Jatty Andriean <jandriea@outlook.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll1 {
+	div-m = <1>;
+	mul-n = <20>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <2>;
+	fracn = <0>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(160)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb3-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
index 6443e08f139..7a45d2c5e62 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
@@ -24,3 +24,9 @@ tests:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay"
     # Build only as HSE not implemened on available boards
     build_only: true
+  drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_fracn_160:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_fracn_160.overlay"
+    # Build only as HSE not implemened on available boards
+    build_only: true
+  drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_fracn_160:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_160.overlay"