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drivers: clock_control: npcx: add MCLKD as i3c source clock

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1. The only valid values of MCLKD clock frequency
   are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
   be equal to or higher than 20Mhz.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
This commit is contained in:
Alvis Sun 2024-04-17 10:28:16 +08:00 • committed by Fabio Baltieri
commit 3ed5f8a948
3 changed files with 26 additions and 1 deletions
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12
soc/nuvoton/npcx/common/soc_clock.h
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@ -105,6 +105,16 @@ struct npcx_clk_cfg {
#endif
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
/* I3C clock divider */
#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
#define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */
#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
#else
#define MCLKD_SL 0 /* I3C_CLK = MCLK */
#endif
/* Get APB clock freq */
#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
@ -158,6 +168,8 @@ struct npcx_clk_cfg {
#else
#define VAL_HFCBCD2 APB3DIV_VAL
#endif /* APB4DIV_VAL */
/* I3C1~I3C3 share the same configuration */
#define VAL_HFCBCD3 MCLKD_SL
/**
* @brief Function to notify clock driver that backup the counter value of