diff --git a/drivers/clock_control/clock_control_npcx.c b/drivers/clock_control/clock_control_npcx.c index dcc4a925c99..eec3604aa77 100644 --- a/drivers/clock_control/clock_control_npcx.c +++ b/drivers/clock_control/clock_control_npcx.c @@ -105,6 +105,9 @@ static int npcx_clock_control_get_subsys_rate(const struct device *dev, case NPCX_CLOCK_BUS_FMCLK: *rate = FMCLK; break; + case NPCX_CLOCK_BUS_MCLKD: + *rate = OFMCLK/(MCLKD_SL + 1); + break; default: *rate = 0U; /* Invalid parameters */ @@ -185,6 +188,13 @@ BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MAX_OFMCLK && (APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0, "Invalid APB4_CLK setting"); #endif +#if defined(CONFIG_I3C_NPCX) +BUILD_ASSERT(OFMCLK / (MCLKD_SL + 1) <= MHZ(50) && + OFMCLK / (MCLKD_SL + 1) >= MHZ(40), + "Invalid MCLKD_SL setting"); +BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(20), + "Invalid PDMA CLK setting"); +#endif static int npcx_clock_control_init(const struct device *dev) { @@ -222,6 +232,7 @@ static int npcx_clock_control_init(const struct device *dev) inst_cdcg->HFCBCD = VAL_HFCBCD; inst_cdcg->HFCBCD1 = VAL_HFCBCD1; inst_cdcg->HFCBCD2 = VAL_HFCBCD2; + inst_cdcg->HFCBCD3 = VAL_HFCBCD3; /* * Power-down (turn off clock) the modules initially for better diff --git a/include/zephyr/dt-bindings/clock/npcx_clock.h b/include/zephyr/dt-bindings/clock/npcx_clock.h index 713a05c5726..d522478d229 100644 --- a/include/zephyr/dt-bindings/clock/npcx_clock.h +++ b/include/zephyr/dt-bindings/clock/npcx_clock.h @@ -20,6 +20,7 @@ #define NPCX_CLOCK_BUS_FMCLK 10 #define NPCX_CLOCK_BUS_FIU0 NPCX_CLOCK_BUS_FIU #define NPCX_CLOCK_BUS_FIU1 11 +#define NPCX_CLOCK_BUS_MCLKD 12 /* clock enable/disable references */ #define NPCX_PWDWN_CTL1 0 @@ -30,6 +31,7 @@ #define NPCX_PWDWN_CTL6 5 #define NPCX_PWDWN_CTL7 6 #define NPCX_PWDWN_CTL8 7 -#define NPCX_PWDWN_CTL_COUNT 8 +#define NPCX_PWDWN_CTL9 8 +#define NPCX_PWDWN_CTL_COUNT 9 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ */ diff --git a/soc/nuvoton/npcx/common/soc_clock.h b/soc/nuvoton/npcx/common/soc_clock.h index d43a70d4529..4ec4c591b04 100644 --- a/soc/nuvoton/npcx/common/soc_clock.h +++ b/soc/nuvoton/npcx/common/soc_clock.h @@ -105,6 +105,16 @@ struct npcx_clk_cfg { #endif #endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */ +/* I3C clock divider */ +#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/ +#define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */ +#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80)) +#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */ +#else +#define MCLKD_SL 0 /* I3C_CLK = MCLK */ +#endif + + /* Get APB clock freq */ #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1)) @@ -158,6 +168,8 @@ struct npcx_clk_cfg { #else #define VAL_HFCBCD2 APB3DIV_VAL #endif /* APB4DIV_VAL */ +/* I3C1~I3C3 share the same configuration */ +#define VAL_HFCBCD3 MCLKD_SL /** * @brief Function to notify clock driver that backup the counter value of