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dts: riscv: litex: remove atomic extention

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remove atomic extention, as the standard
vexriscv has no A.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß 2024-06-11 09:46:03 +02:00 • committed by Alberto Escolar
commit 3a843f924b
2 changed files with 1 additions and 2 deletions
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2
dts/riscv/riscv32-litex-vexriscv.dtsi
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@ -25,7 +25,7 @@
compatible = "litex,vexriscv-standard", "riscv"; compatible = "litex,vexriscv-standard", "riscv";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
riscv,isa = "rv32ima_zicsr_zifencei"; riscv,isa = "rv32im_zicsr_zifencei";
status = "okay"; status = "okay";
}; };
}; };

1
soc/litex/litex_vexriscv/Kconfig
View file

@ -7,7 +7,6 @@ config SOC_LITEX_VEXRISCV
select INCLUDE_RESET_VECTOR select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI select RISCV_ISA_EXT_ZIFENCEI